Datasheet

CDC7005 Functional Block Diagram
1-2
1.1 CDC7005 Functional Block Diagram
/1
/2
/4
/8
/16
PFD
Charge
Pump
HOLD
OPA
SPI LOGIC
MUX_SEL
REF_IN
CTRL_LE
CTRL_DATA
CTRL_CLK
VCXO_IN
VCXO_INB
Y4B
Y4
Y3B
Y3
Y2B
Y2
Y1B
Y1
Y0B
Y0
CP_OUT
STATUS_LOCK
STATUS_VCXO
STATUS_REF
OPA_OUT
OPA_IN
OPA_IP
P Divider
VI
Reference
I_REF
NRESET
NPD
PECL
Latch
PECL
Input
PECL
MUX0
PECL
Latch
PECL
Latch
PECL
Latch
PECL
Latch
PECL
MUX1
PECL
MUX2
PECL
MUX3
PECL
MUX4
PECL
Output
PECL
Output
PECL
Output
PECL
Output
PECL
Output
PECL-TO-
LVTTL
LVCMOS
Input
Prgm Delay
N
+
Prgm Divider
N
Prgm Delay
M
Prgm Divider
M