Datasheet
VCC_Adj_V
VCC_1.8V
VCC_1.8V
1.8V_Vdd_ANA
VCC_Adj_V
Adj_V
1.8V_Vdd_DIG
VCC_Battery
1.8V_Vdd_MSP
VCC_Battery
VBUS_4v3
ADC_0
ADC_1
MSP_EN_Adj
Note:
R73+R72=(Vout/1.25V-1)*R71
C61=((3*10^5)*((R73+R72)+R71))/((R73+R72)*R71)
C50
4.7uF
C50
4.7uF
C66
1uF
C66
1uF
C69
4.7uF
C69
4.7uF
C59
2.2uF
C59
2.2uF
C68
0.1uF
C68
0.1uF
R113
0R0
R113
0R0
C61
15pF
C61
15pF
P3
1.8V_ANA
P3
1.8V_ANA
R78
3.3k
R78
3.3k
C54
0.1uF
C54
0.1uF
L10
50Ohm@100MHz
L10
50Ohm@100MHz
1
2
U5
TPS71219
U5
TPS71219
IN
1
NC
2
OUT1
3
OUT2
4
GND
5
NR
6
FB2/NC
7
EN2
8
FB1/NC
9
EN1
10
T-PAD
11
C58
10nF
C58
10nF
R73
60k
R73
60k
P1
1.8V_DIG
P1
1.8V_DIG
L9
50Ohm@100MHz
L9
50Ohm@100MHz
1
2
J52
JUMPER
J52
JUMPER
1
2
R77
10
R77
10
12
L6
50Ohm@100MHz
L6
50Ohm@100MHz
1
2
L8
50Ohm@100MHz
L8
50Ohm@100MHz
1
2
C56
4.7uF
C56
4.7uF
C64
0.1uF
C64
0.1uF
D8
GREEN
D8
GREEN
1
2
R112
0R0
R112
0R0
L7
50Ohm@100MHz
L7
50Ohm@100MHz
1
2
J51
JUMPER
J51
JUMPER
12
R75
10
R75
10
12
R111
30k1
R111
30k1
R114
0R0
R114
0R0
R70
10
R70
10
12
D4
GREEN
D4
GREEN
1
2
R110
31k6
R110
31k6
J50
JUMPER
J50
JUMPER
12
C57
100nF
C57
100nF
C65
4.7uF
C65
4.7uF
R79
10k
R79
10k
D3
GREEN
D3
GREEN
1
2
C62
1uF
C62
1uF
R115
0R0
R115
0R0
C63
10nF
C63
10nF
C70
1uF
C70
1uF
J71
HEADER2
J71
HEADER2
1
2
C51
1uF
C51
1uF
C53
10nF
C53
10nF
C60
2.2uF
C60
2.2uF
C71
10nF
C71
10nF
C42
4.7uF
C42
4.7uF
P2
Adjustable_V
P2
Adjustable_V
C41
4.7uF
C41
4.7uF
C44
4.7uF
C44
4.7uF
P4
GND
P4
GND
R109
10k
R109
10k
C67
10nF
C67
10nF
C52
4.7uF
C52
4.7uF
D5
RED
D5
RED
12
C72
0.1uF
C72
0.1uF
R76
330
R76
330
12
C77
10u
C77
10u
Schematic
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Figure 4. Schematic – (3 of 3)
8
Quad Sine-Wave Clock Buffer Evaluation Board SCAU040–March 2010
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