Datasheet

LT1074/LT1076
12
sn1074 1074fds
Figure 10. Error Amplifier
DESCRIPTIO S
U
PI
U
A
G
fC
at mid frequencies
A G R at high frequencies
V
m
C
VmC
=
••
=•
2π
Phase shift from the FB pin to the V
C
pin is 90° at mid
frequencies where the external C
C
is controlling gain, then
drops back to 0° (actually 180° since FB is an inverting
input) when the reactance of C
C
is small compared to R
C
.
The low frequency “pole” where the reactance of C
C
is
equal to the output impedance of Q4 and Q6 (r
O
), is:
f
rC
rk
POLE
O
O
=
••
≈Ω
1
2
400
π
Although f
POLE
varies as much as 3:1 due to r
O
variations,
mid-frequency gain is dependent only on G
m
, which is
specified much tighter on the data sheet. The higher
frequency “zero” is determined solely by R
C
and C
C
.
f
RC
ZERO
CC
=
••
1
2π
The error amplifier has asymmetrical peak output current.
Q3 and Q4 current mirrors are unity-gain, but the Q6
mirror has a gain of 1.8 at output null and a gain of 8 when
the FB pin is high (Q1 current = 0). This results in a
maximum positive output current of 140µA and a maxi-
mum negative (sink) output current of ≅1.1mA. The asym-
metry is deliberate—it results in much less regulator
output overshoot during rapid start-up or following the
release of an output overload. Amplifier offset is kept low
by area scaling Q1 and Q2 at 1.8:1.
Amplifier swing is limited by the internal 5.8V supply for
positive outputs and by D1 and D2 when the output goes
low. Low clamp voltage is approximately one diode drop
(≈0.7V – 2mV/°C).
Note that both the FB pin and the V
C
pin have other internal
connections. Refer to the frequency shifting and synchro-
nizing discussions.
140 Aµ
Q1
LT1074 • PD11
Q2
FB
V
50 Aµ
90 A
µ
Q6
300
C
Q4
5.8V
C
C
R
C
Q3
50 Aµ
2.21V
EXTERNAL
FREQUENCY
COMPENSATION
90 Aµ
D1
90 Aµ
Ω
D2
X1.8
ALL CURRENTS SHOWN ARE AT NULL CONDITION