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CD74HCT4543

BCD-TO-7 SEGMENT LATCH/DECODER/DRIVER

SCHS281A – REVISED MAY 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4.5-V to 5.5-V V

Operation

Input Latches for BCD Code Storage

Blanking Capability

Phase Input for Complementing Outputs

Fanout (Over Temperature Range)

– Standard Outputs – 10 LSTTL Loads

Balanced Propagation Delay and Transition

Times

Significant Power Reduction, Compared to

LSTTL Logic ICs

Direct LSTTL Input Logic Compatibility,

= 0.8 V Maximum, V

= 2 V Minimum

CMOS Input Compatibility, I

≤ 1 µA at V

description/ordering information

The CD74HCT4543 high-speed silicon-gate is a BCD-to-7 segment latch/decoder/driver designed primarily for

directly driving liquid-crystal displays. While the latch enable (LD) is low, the latches are enabled to store the

BCD inputs. When the latch enable is high, the latches are disabled, making the outputs transparent to the BCD

inputs. The device has an active-high blanking input (BI) and a phase input (PH) to which a square wave is

applied for liquid-crystal applications. This square wave also is applied to the backplane of the liquid-crystal

display.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

–55°C to 125°C PDIP – E Tube CD74HCT4543E CD74HCT4543E

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB

design guidelines are available at www.ti.com/sc/package.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

GND

(TOP VIEW)

BCD

Inputs

7-Segment

Outputs

E PACKAGE

01 23 456789

DISPLAY

Summary of content (10 pages)

PAGE 1
CD74HCT4543 BCD-TO-7 SEGMENT LATCH/DECODER/DRIVER SCHS281A – REVISED MAY 2003 D D D D D D D D D E PACKAGE (TOP VIEW) 4.5-V to 5.5-V VCC Operation Input Latches for BCD Code Storage Blanking Capability Phase Input for Complementing Outputs Fanout (Over Temperature Range) – Standard Outputs – 10 LSTTL Loads Balanced Propagation Delay and Transition Times Significant Power Reduction, Compared to LSTTL Logic ICs Direct LSTTL Input Logic Compatibility, VIL = 0.
PAGE 2
CD74HCT4543 BCD-TO-7 SEGMENT LATCH/DECODER/DRIVER SCHS281A – REVISED MAY 2003 FUNCTION TABLE LD BI PH D3 D2 D1 D0 a b c d e f g Display X H L X X X X L L L L L L L Blank H L L L L L L H H H H H H L 0 H L L L L L H L H H L L L L 1 H L L L L H L H H L H H L H 2 H L L L L H H H H H H L L H 3 H L L L H L L L H H L L H H 4 H L L L H L H H L H H L H H 5 H L L L H H L H L H H H H H
PAGE 3
CD74HCT4543 BCD-TO-7 SEGMENT LATCH/DECODER/DRIVER SCHS281A – REVISED MAY 2003 logic diagram 7 BI 9 a 5 D0 D0 Q0 10 Latch LD LD LD LD Q0 11 3 D D1 b c Q1 Latch LD LD LD LD 12 Q1 LD Dn 2 D2 Q2 D2 LD 4 LD LD Qn LD Q LD n Latch LD d ≡ Dn Qn P n Qn LD LD P n Q2 13 e LD D3 Q3 D3 Latch 15 Q3 LD LD LD LD f 1 LD LD 14 LD g 6 PH POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3
PAGE 4
CD74HCT4543 BCD-TO-7 SEGMENT LATCH/DECODER/DRIVER SCHS281A – REVISED MAY 2003 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input diode current, IIK (VI < –0.5 V or VI > VCC + 0.5 V) ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output diode current, IOK (VO < –0.5 V or VO > VCC + 0.
PAGE 5
CD74HCT4543 BCD-TO-7 SEGMENT LATCH/DECODER/DRIVER SCHS281A – REVISED MAY 2003 HCT INPUT LOADING TABLE INPUT UNIT LOADS† D0, D1, D2 1 D3, BI 0.5 PH 1.25 LD 1.5 † Unit Load is ∆ICC limit specified in electrical characteristics table, e.g., 360 µA maximum at 25°C. timing requirements over recommended operating free-air temperature range VCC = 4.
PAGE 6
CD74HCT4543 BCD-TO-7 SEGMENT LATCH/DECODER/DRIVER SCHS281A – REVISED MAY 2003 PARAMETER MEASUREMENT INFORMATION VCC Test Point From Output Under Test PARAMETER S1 ten RL = 1 kΩ tdis CL (see Note A) S2 S1 S2 tPZH Open Closed tPZL Closed Open tPHZ Open Closed tPLZ Closed Open Open Open tpd or tt tw LOAD CIRCUIT VCC Input 50% VCC 50% VCC 0V VOLTAGE WAVEFORMS PULSE DURATION CLR Input VCC Reference Input VCC 50% VCC 50% VCC 0V 0V tsu trec Data 50% Input 10% VCC 50% VCC
PAGE 7
CD74HCT4543 BCD-TO-7 SEGMENT LATCH/DECODER/DRIVER SCHS281A – REVISED MAY 2003 APPLICATION CIRCUITS Appropriate Voltage HCT4543 Output PH One of Seven Segments Common Backplane HCT4543 ÉÉÉÉÉ ÉÉÉÉÉ Output PH GND Square Wave: GND to VCC Figure 2. Connection to Liquid-Crystal Display (LCD) Figure 3. Connection to Incandescent Display Appropriate Voltage HCT4543 HCT4543 Output Output PH GND To Filament Supply PH GND GND or Appropriate Voltage Below GND Figure 4.
PAGE 8
PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty CD74HCT4543E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HCT4543EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.