Datasheet

9
SIG
IN
, COMP
IN
DC Coupled
Low-Level Input
Voltage
V
IL
- - 4.5 to
5.5
- - 0.8 - 0.8 - 0.8 V
PCP
OUT
, PCn OUT
High-Level Output
Voltage
CMOS Loads
V
OH
V
IL
or V
IH
- 4.5 4.4 - - 4.4 - 4.4 - V
PCP
OUT
, PCn OUT
High-Level Output
Voltage
TTL Loads
V
OH
V
IL
or V
IH
- 4.5 3.98 - - 3.84 - 3.7 - V
PCP
OUT
, PCn OUT
Low-Level Output
Voltage
CMOS Loads
V
OL
V
IL
or V
IH
- 4.5 - - 0.1 - 0.1 - 0.1 V
PCP
OUT
, PCn OUT
Low-Level Output
Voltage
TTL Loads
V
OL
V
IL
or V
IH
- 4.5 - - 0.26 - 0.33 - 0.4 V
SIG
IN
, COMP
IN
Input
Leakage Current
I
I
Any
Voltage
Between
V
CC
and
GND
- 5.5 - - ±30 ±38 ±45 µA
PC2
OUT
Three-State
Off-State Current
I
OZ
V
IL
or V
IH
- 5.5 - - ±0.5 ±5- -±10 µA
SIG
IN
, COMP
IN
Input
Resistance
R
I
V
I
at Self-Bias
Operation Point:
∆V
I
, 0.5V,
See Figure 10
4.5 - 250 - - - - - kΩ
DEMODULATOR SECTION
Resistor Range R
S
at R
S
> 300kΩ
Leakage Current
Can Influence
V
DEM OUT
4.5 5 - 300 - - - - kΩ
Offset Voltage VCO
IN
to V
DEM
V
OFF
V
I
= V
VCO IN
=
Values taken over
R
S
Range
See Figure 24
4.5 - ±20 - - - - - mV
Dynamic Output
Resistance at
DEM
OUT
R
D
V
DEM OUT
= 4.5 - 25 - - - - - Ω
Quiescent Device
Current
I
CC
V
CC
or
GND
- 5.5 - - 8 - 80 - 160 µA
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I
CC
Note 6
V
CC
-2.1
Excluding
Pin 5
- 4.5 to
5.5
- 100 360 - 450 - 490 µA
NOTES:
4. The value for R1 and R2 in parallel should exceed 2.7kΩ.
5. The maximum operating voltage can be as high as V
CC
-0.9V, however, this may result in an increased offset voltage.
6. For dual-supply systems theoretical worst case (V
I
= 2.4V, V
CC
= 5.5V) specification is 1.8mA.
DC Electrical Specifications (Continued)
PARAMETER SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C -40
o
C TO 85
o
C -55
o
C TO 125
o
C
UNITSV
I
(V) I
O
(mA) MIN TYP MAX MIN MAX MIN MAX
V
CC
2
V
CC
2
CD74HC4046A, CD74HCT4046A