Datasheet

4
The frequency capture range (2f
C
) is defined as the fre-
quency range of input signals on which the PLL will lock if it
was initially out-of-lock. The frequency lock range (2f
L
) is
defined as the frequency range of input signals on which the
loop will stay locked if it was initially in lock. The capture
range is smaller or equal to the lock range.
With PC1, the capture range depends on the low-pass filter
characteristics and can be made as large as the lock range.
This configuration retains lock behavior even with very noisy
input signals. Typical of this type of phase comparator is that
it can lock to input frequencies close to the harmonics of the
VCO center frequency.
Phase Comparator 2 (PC2)
This is a positive edge-triggered phase and frequency detec-
tor. When the PLL is using this comparator, the loop is con-
trolled by positive signal transitions and the duty factors of
SIG
IN
and COMP
IN
are not important. PC2 comprises two
D-type flip-flops, control-gating and a three-state output
stage. The circuit functions as an up-down counter (Figure
1) where SIG
IN
causes an up-count and COMP
IN
a down-
count. The transfer function of PC2, assuming ripple (f
r
= f
i
)
is suppressed, is:
V
DEMOUT
= (V
CC
/4π) (φSIG
IN
- φCOMP
IN
) where V
DE-
MOUT
is the demodulator output at pin 10; V
DEMOUT
=
V
PC2OUT
(via low-pass filter).
The average output voltage from PC2, fed to the VCO via the
low-pass filter and seen at the demodulator output at pin 10
(V
DEMOUT
), is the resultant of the phase differences of
SIG
IN
and COMP
IN
as shown in Figure 4. Typical waveforms
for the PC2 loop locked at f
o
are shown in Figure 5.
When the frequencies of SIG
IN
and COMP
IN
are equal but
the phase of SIG
IN
leads that of COMP
IN
, the p-type output
driver at PC2
OUT
is held “ON” for a time corresponding to
the phase difference (φ
DEMOUT
). When the phase of SIG
IN
lags that of COMP
IN
, the n-type driver is held “ON”.
When the frequency of SIG
IN
is higher than that of COMP
IN
,
the p-type output driver is held “ON” for most of the input sig-
nal cycle time, and for the remainder of the cycle both n- and
p-type drivers are “OFF” (three-state). If the SIG
IN
frequency
is lower than the COMP
IN
frequency, then it is the n-type
driver that is held “ON” for most of the cycle. Subsequently,
the voltage at the capacitor (C2) of the low-pass filter con-
nected to PC2
OUT
varies until the signal and comparator
inputs are equal in both phase and frequency. At this stable
FIGURE 2. PHASE COMPARATOR 1: AVERAGE OUTPUT
VOLTAGE vs INPUT PHASE DIFFERENCE:
V
DEMOUT
= V
PC1OUT
= (V
CC
/π) (φSIG
IN
- φCOM-
P
IN
); φ
DEMOUT
=(φSIG
IN
- φCOMP
IN
)
V
CC
V
DEMOUT (AV)
1/2 V
CC
0
0
o
90
o
φ
DEMOUT
180
o
FIGURE 3. TYPICAL WAVEFORMS FOR PLL USING PHASE
COMPARATOR 1, LOOP LOCKED AT f
o
SIG
IN
COMP
IN
VCO
OUT
PC1
OUT
VCO
IN
V
CC
GND
FIGURE 4. PHASE COMPARATOR 2: AVERAGE OUTPUT
VOLTAGE vs INPUT PHASE DIFFERENCE:
V
DEMOUT
= V
PC2OUT
= (V
CC
/4π) (φSIG
IN
- φCOM-
P
IN
); φ
DEMOUT
=(φSIG
IN
- φCOMP
IN
)
V
CC
V
DEMOUT (AV)
1/2 V
CC
0
-360
o
0
o
φ
DEMOUT
360
o
FIGURE 5. TYPICAL WAVEFORMS FOR PLL USING PHASE
COMPARATOR 2, LOOP LOCKED AT f
o
SIG
IN
COMP
IN
VCO
OUT
PC2
OUT
VCO
IN
V
CC
GND
PCP
OUT
HIGH IMPEDANCE OFF - STATE
CD74HC4046A, CD74HCT4046ACD74HC4046A, CD74HCT4046A