Datasheet

3
General Description
VCO
The VCO requires one external capacitor C1 (between C1
A
and C1
B
) and one external resistor R1 (between R
1
and
GND) or two external resistors R1 and R2 (between R
1
and
GND, and R
2
and GND). Resistor R1 and capacitor C1
determine the frequency range of the VCO. Resistor R2
enables the VCO to have a frequency offset if required. See
logic diagram, Figure 1.
The high input impedance of the VCO simplifies the design
of low-pass filters by giving the designer a wide choice of
resistor/capacitor ranges. In order not to load the low-pass
filter, a demodulator output of the VCO input voltage is pro-
vided at pin 10 (DEM
OUT
). In contrast to conventional tech-
niques where the DEM
OUT
voltage is one threshold voltage
lower than the VCO input voltage, here the DEM
OUT
voltage
equals that of the VCO input. If DEM
OUT
is used, a load
resistor (R
S
) should be connected from DEM
OUT
to GND; if
unused, DEM
OUT
should be left open. The VCO output
(VCO
OUT
) can be connected directly to the comparator
input (COMP
IN
), or connected via a frequency-divider. The
VCO output signal has a guaranteed duty factor of 50%. A
LOW level at the inhibit input (INH) enables the VCO and
demodulator, while a HIGH level turns both off to minimize
standby power consumption.
Phase Comparators
The signal input (SIG
IN
) can be directly coupled to the self-
biasing amplifier at pin 14, provided that the signal swing is
between the standard HC family input logic levels. Capaci-
tive coupling is required for signals with smaller swings.
Phase Comparator 1 (PC1)
This is an Exclusive-OR network. The signal and comparator
input frequencies (f
i
) must have a 50% duty factor to obtain
the maximum locking range. The transfer characteristic of
PC1, assuming ripple (f
r
= 2f
i
) is suppressed, is:
V
DEMOUT
= (V
CC
/π) (φSIG
IN
- φCOMP
IN
) where V
DEMOUT
is the demodulator output at pin 10; V
DEMOUT
= V
PC1OUT
(via low-pass filter).
The average output voltage from PC1, fed to the VCO input
via the low-pass filter and seen at the demodulator output at
pin 10 (V
DEMOUT
), is the resultant of the phase differences
of signals (SIG
IN
) and the comparator input (COMP
IN
) as
shown in Figure 2. The average of V
DEM
is equal to 1/2 V
CC
when there is no signal or noise at SIG
IN
, and with this input
the VCO oscillates at the center frequency (f
o
). Typical wave-
forms for the PC1 loop locked at f
o
are shown in Figure 3.
FIGURE 1. LOGIC DIAGRAM
DEM
OUT
R2
12
R1
R5
11
10
C1
R3
C2
PC2
OUT
13
p
n
GND
V
CC
PCP
OUT
1
15
2
PC3
OUT
PC1
OUT
DOWN
R
D
Q
Q
D
CP
R
D
Q
Q
D
CP
UP
V
CC
V
CC
R
D
Q
Q
S
D
INH
59
VCO
IN
VCO
-
+
VCO
OUT
COMP
IN
-
+
SIG
IN
C1
B
C1
A
V
REF
R2
R1
674314
-
+
CD74HC4046A, CD74HCT4046ACD74HC4046A, CD74HCT4046A