Datasheet

20
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SEMICONDUCTOR
PLL Conditions with
No Signal at the
SIG
IN
Input
PC1 VCO adjusts to f
o
with φ
DEMOUT
= 90
o
and V
VCOIN
= 1/2 V
CC
(see Figure 2)
PC2 VCO adjusts to f
MIN
with φ
DEMOUT
= -360
o
and V
VCOIN
= 0V (see Figure 4)
PC3 VCO adjusts to f
MAX
with φ
DEMOUT
= 360
o
and V
VCOIN
= V
CC
(see Figure 6)
PLL Frequency
Capture Range
PC1, PC2 or PC3 Loop Filter Component Selection
PLL Locks on
Harmonics at Center
Frequency
PC1 or PC3 Yes
PC2 No
Noise Rejection at
Signal Input
PC1 High
PC2 or PC3 Low
AC Ripple Content
when PLL is Locked
PC1 f
r
= 2f
i
, large ripple content at φ
DEMOUT
= 90
o
PC2 f
r
= f
i
, small ripple content at φ
DEMOUT
= 0
o
PC3 f
r
= fSIG
IN
, large ripple content at φ
DEMOUT
= 180
o
SUBJECT
PHASE
COMPARATOR DESIGN CONSIDERATIONS
A small capture range (2f
c
) is obtained if τ > 2f
c
≈ 1/π (2πf
L
/τ.)
1/2
FIGURE 47. SIMPLE LOOP FILTER FOR PLL WITHOUT OFFSET
(A) τ = R3 x C2
(B) AMPLITUDE CHARACTERISTIC (C) POLE-ZERO DIAGRAM
R3
C2
INPUT OUTPUT
|F
(j
ω
)
|
ω
-1/
τ
FIGURE 48. SIMPLE LOOP FILTER FOR PLL WITH OFFSET
(A) τ1 = R3 x C2;
(B) AMPLITUDE CHARACTERISTIC (C) POLE-ZERO DIAGRAM
|F
(j
ω
)
|
ω
-1/
τ
2
R3
C2
INPUT OUTPUT
τ2 = R4 x C2;
τ3 = (R3 + R4) x C2
-1/
τ
3
m
1/
τ
3
1/
τ
2
R4
m =
R4
R3 + R4
CD74HC4046A, CD74HCT4046A