Datasheet

9
Propagation Delay,
Sn → Y, Y
t
PLH
, t
PHL
C
L
= 50pF 4.5 - 59 74 89 ns
C
L
= 15pF 5 25 - - - ns
Propagation Delay,
LE → Y, Y
t
PLH
, t
PHL
C
L
= 50pF 4.5 - 63 79 94 ns
C
L
= 15pF 5 25 - - - ns
Output Disabling Time,
OEn to Y, Y
t
PLZ
, t
PHZ
C
L
= 50pF 4.5 - 33 41 50 ns
C
L
= 15pF 5 13, 16 - - - ns
Output Disabling Time,
OE3 to Y, Y
t
PLZ
, t
PHZ
C
L
= 50pF 4.5 - 39 49 59 ns
C
L
= 15pF 5 13, 16 - - - ns
Output Enabling Time,
OEn to Y, Y
t
PZL
, t
PZH
C
L
= 50pF 4.5 - 34 43 51 ns
C
L
= 15pF 5 14 - - - ns
Output Enabling Time,
OE3 to Y, Y
t
PZL
, t
PZH
C
L
= 50pF 4.5 - 34 43 51 ns
C
L
= 15pF 5 14 - - - ns
Output Transition Time t
TLH
, t
THL
C
L
= 50pF 4.5 - 12 15 18 ns
Input Capacitance C
IN
---1010 10pF
Three-State Capacitance C
O
---2020 20pF
Power Dissipation
Capacitance
(Notes 4, 5)
C
PD
- 5 92 - - - pF
NOTES:
4. C
PD
is used to determine the dynamic power consumption, per device.
5. P
D
= V
CC
2
(C
PD
+ C
L
) where f
i
= Input Frequency, C
L
= Output Load Capacitance, V
CC
= Supply Voltage.
Switching Specifications Input t
r
, t
f
= 6ns (Continued)
PARAMETER SYMBOL
TEST
CONDITIONS V
CC
(V)
25
o
C -40
o
C TO 85
o
C
-55
o
C TO
125
o
C
UNITSTYP MAX MAX MAX
Test Circuits and Waveforms
NOTE: Outputs should be switching from 10% V
CC
to 90% V
CC
in
accordance with device truth table. For f
MAX
, input duty cycle = 50%.
FIGURE 2. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
NOTE: Outputs should be switching from 10% V
CC
to 90% V
CC
in
accordance with device truth table. For f
MAX
, input duty cycle = 50%.
FIGURE 3. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
CLOCK
90%
50%
10%
GND
V
CC
t
r
C
L
t
f
C
L
50%
50%
t
WL
t
WH
10%
t
WL
+ t
WH
=
fC
L
I
CLOCK
2.7V
1.3V
0.3V
GND
3V
t
r
C
L
= 6ns
t
f
C
L
= 6ns
1.3V
1.3V
t
WL
t
WH
0.3V
t
WL
+ t
WH
=
fC
L
I
CD54HC354, CD74HC354, CD74HCT354