Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Multiplexer Multiplexer Single supply PDIP 20

Semiconductor

Features

• HC/HCT354

- Transparent Data and Select Latches

• Buffered Inputs

• Three-State Complementary Outputs

• Bus Line Driving Capability

• Typical Propagation Delay: V

= 5V, C

= 15pF,

= 25

- Data to Output = 18ns

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

C to 125

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, N

= 30% of V

at V

= 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

= 0.8V (Max), V

= 2V (Min)

- CMOS Input Compatibility, I

≤ 1µA at V

, V

Description

The CD54HC354, CD74HC354, and CD74HCT354 are data

selectors/multiplexers that select one of eight sources. In both

types, the data select bits S0, S1 and S2 are stored in

transparent latches that are enabled by a low latch enable

input,

LE.

In the HC/HCT354 the data enable input,

E, controls

transparent latches that pass data to the outputs when

Eis

high and latches in new data when

E is low.

In both types the three-state outputs are controlled by three

output-enable inputs

OE1, OE2, and OE3.

Pinout

CD54HC354

(CERDIP)

CD74HC354, CD74HCT354

(PDIP)

TOP VIEW

Ordering Information

PART NUMBER

TEMP. RANGE

(

C) PACKAGE

CD54HC354F3A -55 TO 125 20 Ld CERDIP

CD74HC354E -55 to 125 20 Ld PDIP

CD74HCT354E -55 to 125 20 Ld PDIP

GND

OE3

OE2

OE1

SCHS277D - November 1997 - Revised May 2003

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54HC354, CD74HC354,

CD74HCT354

8-Line to 1-Line Data Selector/Multiplexer/Register

With 3-State Outputs

[ /Title

(CD74

HC354

CD74

HCT35

Sub-

ect

(High

Speed

CMOS

Logic

8-Input

Multip

lexer/

Regis-

Summary of content (15 pages)

PAGE 1
[ /Title (CD74 HC354 , CD74 HCT35 4) /Subject (High Speed CMOS Logic 8-Input Multip lexer/ Regis- CD54HC354, CD74HC354, CD74HCT354 Semiconductor 8-Line to 1-Line Data Selector/Multiplexer/Register With 3-State Outputs SCHS277D - November 1997 - Revised May 2003 Features Description • HC/HCT354 - Transparent Data and Select Latches • Buffered Inputs • Three-State Complementary Outputs • Bus Line Driving Capability • Typical Propagation Delay: VCC = 5V, CL = 15pF, TA = 25oC - Data to Output = 18ns • Fano
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CD54HC354, CD74HC354, CD74HCT354 Functional Diagram S0 14 S1 13 S2 12 D0 D1 D2 D3 D4 D5 D6 D7 8 19 7 Y 6 5 4 3 18 2 Y 1 11 LE 15 OE1 16 OE2 17 OE3 9 E TRUTH TABLE INPUTS ENABLE DATA SELECT (NOTE 1 ) OUTPUT ENABLES OUTPUTS S2 S1 S0 E OE1 OE2 OE3 Y Y X X X X H X X Z Z X X X X X H X Z Z X X X X X X L Z Z L L L L L L H D0 D0 L L L H L L H D0n D0n L L H L L L H D1 D1 L L H H L L H D1n D1n L H L L L L H D2 D2 L
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CD54HC354, CD74HC354, CD74HCT354 TRUTH TABLE (Continued) INPUTS ENABLE DATA SELECT (NOTE 1 ) OUTPUT ENABLES OUTPUTS S2 S1 S0 E OE1 OE2 OE3 Y Y H H H L L L H D7 D7 H H H H L L H D7n D7n H = High Voltage Level (Steady State); L = Low Voltage Level (Steady State); X = Don’t Care; Z = High Impedance State (Off State); D0n...D7n = the level of steady-state inputs D0 through D7, respectively, before the most recent low-to-high transition of data control. NOTE: 1.
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CD54HC354, CD74HC354, CD74HCT354 Logic Diagram 15 OE1 16 OE2 OE3 1 OF 8 LATCHES VCC 17 P E 8 (7, 6, 5, 4, 3, 2, 1) E D0 P N 18 Y N P N GND E P N E E E VCC P 19 Y N 9 TO 7 OTHER LATCHES E OTHER 7 LATCH OUTPUTS CONNECT HERE SEL0 GND TO OTHER 7 LATCHES SEL0 SEL1 SEL2 SEL3 20 VCC 10 GND LE P N LE 14 S0 13 S1 12 S2 P N LE LE LE LE P N SL0 SL0 P N LE LE LE LE P N SL1 SL1 LE P N SL2 SL2 LE 11 LE LE LE FIGURE 1.
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CD54HC354, CD74HC354, CD74HCT354 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .
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CD54HC354, CD74HC354, CD74HCT354 DC Electrical Specifications (Continued) TEST CONDITIONS SYMBOL VI (V) Quiescent Device Current ICC VCC or GND 0 Three-State Leakage Current IOZ VIL or VIH High Level Input Voltage VIH Low Level Input Voltage High Level Output Voltage CMOS Loads PARAMETER 25oC IO (mA) VCC (V) -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 6 - - 8 - 80 - 160 µA VO = VCC or GND 6 - - ±0.5 - ±5.0 - ±10 µA - - 4.5 to 5.
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CD54HC354, CD74HC354, CD74HCT354 Prerequisite For Switching Specifications PARAMETER 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tPLH, tPHL - 2 80 - - 100 - 120 - ns 4.5 16 - - 20 - 24 - ns 6 14 - - 17 - 20 - ns 2 80 - - 100 - 120 - ns 4.5 16 - - 20 - 24 - ns 6 14 - - 17 - 20 - ns 2 50 - - 65 - 75 - ns 4.
PAGE 8
CD54HC354, CD74HC354, CD74HCT354 Switching Specifications PARAMETER Propagation Delay, Sn → Y, Y Propagation Delay, LE → Y, Y Output Disabling Time, OEn to Y, Y Output Disabling Time, OE3 to Y, Y Output Enabling Time, OEn to Y, Y Output Enabling Time, OE3 to Y, Y Output Transition Time Input tr, tf = 6ns (Continued) SYMBOL TEST CONDITIONS tPLH, tPHL CL = 50pF tPLH, tPHL tPLZ, tPHZ tPLZ, tPHZ tPZL, tPZH tPZL, tPZH tTLH, tTHL 25oC -40oC TO 85oC -55oC TO 125oC VCC (V) TYP MAX MAX MAX
PAGE 9
CD54HC354, CD74HC354, CD74HCT354 Switching Specifications Input tr, tf = 6ns (Continued) SYMBOL TEST CONDITIONS Propagation Delay, Sn → Y, Y tPLH, tPHL Propagation Delay, LE → Y, Y tPLH, tPHL Output Disabling Time, OEn to Y, Y tPLZ, tPHZ Output Disabling Time, OE3 to Y, Y tPLZ, tPHZ Output Enabling Time, OEn to Y, Y tPZL, tPZH Output Enabling Time, OE3 to Y, Y tPZL, tPZH Output Transition Time tTLH, tTHL PARAMETER 25oC -40oC TO 85oC -55oC TO 125oC VCC (V) TYP MAX MAX MAX UNITS CL
PAGE 10
CD54HC354, CD74HC354, CD74HCT354 Test Circuits and Waveforms tr = 6ns (Continued) tf = 6ns 90% 50% 10% INPUT GND tTLH 90% INVERTING OUTPUT tPHL FIGURE 4. HC AND HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC trCL VCC 90% GND tH(H) 3V 2.7V 1.3V 0.3V GND tH(H) tH(L) VCC DATA INPUT DATA INPUT 50% tH(L) 3V 1.3V 1.3V 1.3V GND tSU(H) tSU(H) tSU(L) tTLH 90% OUTPUT tTHL 90% 50% 10% tTLH 90% 1.3V OUTPUT tREM 3V SET, RESET OR PRESET GND tTHL 1.3V 10% FIGURE 6.
PAGE 11
CD54HC354, CD74HC354, CD74HCT354 Test Circuits and Waveforms 6ns (Continued) 6ns OUTPUT DISABLE tr VCC 90% 50% 10% OUTPUTS ENABLED OUTPUT HIGH TO OFF 50% OUTPUTS DISABLED FIGURE 8. HC THREE-STATE PROPAGATION DELAY WAVEFORM OTHER INPUTS TIED HIGH OR LOW OUTPUT DISABLE IC WITH THREESTATE OUTPUT GND 1.3V tPZH 90% OUTPUTS ENABLED OUTPUTS ENABLED 0.3 10% tPHZ tPZH 90% 3V tPZL tPLZ OUTPUT LOW TO OFF 50% OUTPUT HIGH TO OFF 6ns GND 10% tPHZ tf 2.7 1.
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PACKAGE OPTION ADDENDUM www.ti.
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