Datasheet

2
Pinout
CD54HC138, CD54HCT138, CD54HC238, CD54HCT238
(CERDIP)
CD74HC138, CD74HCT138, CD74HCT238
(PDIP, SOIC)
CD74HC238
(PDIP, SOIC, SOP, TSSOP)
TOP VIEW
Signal names in parentheses are for ’HC138 and ’HCT138.
Functional Diagram
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
A0
A1
A2
E1
E2
E3
GND
(Y7) Y7
V
CC
Y1 (Y1)
Y2 (
Y2)
Y3 (
Y3)
Y4 (
Y4)
Y5 (
Y5)
Y6 (
Y6)
Y0 (
Y0)
15
14
13
12
10
7
9
11
1
2
3
5
6
4
E3
E2
E1
A2
A1
A0 Y0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
HC/HCT
238
HC/HCT
138
TRUTH TABLE ’HC138, ’HCT138
INPUTS
OUTPUTSENABLE ADDRESS
E3 E2 E1 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
XXHXXXHHHHHHHH
LXXXXXHHHHHHHH
XHXXXXHHHHHHHH
HLLLLLLHHHHHHH
HL L L LHHLHHHHHH
HL L LHLHHLHHHHH
HL L LHHHHHLHHHH
HL LHL LHHHHLHHH
HL LHLHHHHHHLHH
HL LHHLHHHHHHLH
HL LHHHHHHHHHHL
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care
TRUTH TABLE ’HC238, ’HCT238
INPUTS
OUTPUTSENABLE ADDRESS
E3 E2 E1 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
XXHXXXLLLLLLLL
LXXXXXLLLLLLLL
XHXXXXLLLLLLLL
HLLLLLHLLLLLLL
HLLLLHLHLLLLLL
HLLLHLLLHLLLLL
HLLLHHLLLHLLLL
HLLHLLLLLLHLLL
HLLHLHLLLLLHLL
HLLHHLLLLLLLHL
HLLHHHLLLLLLLH
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care
CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238