Datasheet

2
Pinout
CD54HC237 (CERDIP)
CD74HC137 (PDIP, TSSOP)
CD74HCT137 (PDIP, SOIC)
CD74HC237 (PDIP, SOIC, SOP, TSSOP)
CD74HCT237 (PDIP)
TOP VIEW
Functional Diagram
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
A
0
A
1
A
3
LE
OE
1
OE
0
GND
Y
7
V
CC
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
0
15
14
13
12
10
7
9
11
1
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
3
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
237 137
6
2
4
5
A
0
A
1
A
2
LE
OE
1
OE
0
3-BIT
LATCH
1 OF 8
DECODER
GND = 8
V
CC
= 16
HC/HCT HC/HCT
’HC137, ’HCT137 TRUTH TABLE
INPUTS OUTPUTS
LE OE
0
OE
1
A
2
A
1
A
0
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
XXHXXXHHHHHHHH
XLXXXXHHHHHHHH
LHLLLLLHHHHHHH
LHL L LHHLHHHHHH
LHL LHLHHLHHHHH
LHL LHHHHHLHHHH
LHLHL LHHHHLHHH
LHLHLHHHHHHLHH
LHLHHLHHHHHHLH
LHLHHHHHHHHHHL
H H L X X X Depends upon the address previously applied while LE was at a logic low.
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care
’HC237, ’HCT237 TRUTH TABLE
INPUTS OUTPUTS
LE OE
0
OE
1
A
2
A
1
A
0
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
XXHXXXLLLLLLLL
XLXXXXLLLLLLLL
LHLLLLHLLLLLLL
LHLLLHLHLLLLLL
LHLLHLLLHLLLLL
LHLLHHLLLHLLLL
LHLHLLLLLLHLLL
LHLHLHLLLLLHLL
LHLHHLLLLLLLHL
LHLHHHLLLLLLLH
H H L X X X Depends upon the address previously applied while LE was at a logic low.
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care
CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237