Datasheet

4
HCT TYPES
High Level Input
Voltage
V
IH
- - 4.5 to
5.5
2--2 - 2 - V
Low Level Input
Voltage
V
IL
- - 4.5 to
5.5
- - 0.8 - 0.8 - 0.8 V
High Level Output
Voltage
CMOS Loads
V
OH
V
IH
or V
IL
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
High Level Output
Voltage
TTL Loads
-4 4.5 3.98 - - 3.84 - 3.7 - V
Low Level Output
Voltage
CMOS Loads
V
OL
V
IH
or V
IL
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage
TTL Loads
4 4.5 - - 0.26 - 0.33 - 0.4 V
Input Leakage
Current
I
I
V
CC
and
GND
0 5.5 - ±0.1 - ±1-±1 µA
Quiescent Device
Current
I
CC
V
CC
or
GND
0 5.5 - - 8 - 80 - 160 µA
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I
CC
(Note 2)
V
CC
-2.1
- 4.5 to
5.5
- 100 360 - 450 - 490 µA
NOTE:
2. For dual-supply systems theoretical worst case (V
I
= 2.4V, V
CC
= 5.5V) specification is 1.8mA.
DC Electrical Specifications (Continued)
PARAMETER SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C -40
o
C TO 85
o
C -55
o
C TO 125
o
C
UNITSV
I
(V) I
O
(mA) MIN TYP MAX MIN MAX MIN MAX
HCT Input Loading Table
INPUT UNIT LOADS
I
1
, I
2
, I
3
, I
6
, I
7
1.1
I
4
, I
5
, I
8
, I
9
1.5
NOTE: Unit Load is ∆I
CC
limit specified in DC Electrical Table, e.g.,
360µA max at 25
o
C.
Switching Specifications Input t
r
, t
f
= 6ns
PARAMETER SYMBOL
TEST
CONDITIONS V
CC
(V)
25
o
C -40
o
C TO 85
o
C -55
o
C TO 125
o
C
UNITSMIN TYP MAX MIN MAX MIN MAX
HC TYPES
Propagation Delay,
Input to Output (Figure 1)
t
PLH,
t
PHL
C
L
= 50pF 2 - - 160 - 200 - 240 ns
4.5 - - 32 - 40 - 48 ns
5 - 13 - - - - - ns
6 - - 27 - 34 - 41 ns
Transition Times
(Figure 1)
t
TLH
, t
THL
C
L
= 50pF 2 - - 75 - 95 - 110 ns
4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns
Input Capacitance C
IN
- - - - 10 - 10 - 10 pF
CD54HC147, CD74HC147, CD74HCT147