Datasheet

6
Test Circuits and Waveforms
FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
FIGURE 3. HYSTERESIS DEFINITION, CHARACTERISTIC, AND TEST SET-UP
t
PHL
t
PLH
t
THL
t
TLH
90%
50%
10%
50%
10%
INVERTING
OUTPUT
INPUT
GND
V
CC
t
r
= 6ns t
f
= 6ns
90%
t
PHL
t
PLH
t
THL
t
TLH
2.7V
1.3V
0.3V
1.3V
10%
INVERTING
OUTPUT
INPUT
GND
3V
t
r
= 6ns
t
f
= 6ns
90%
V
CC
V
l
GND
V
CC
V
O
GND
V
CC
V
l
V
O
V
O
V
H
V
H
= V
+
T
- V
-
T
-
T
V
+
T
V
V
H
V
l
-
T
V
+
T
V
CD54HC132, CD74HC132, CD54HCT132, CD74HCT132