Datasheet

6
CP Frequency f
MAX
CL = 15pF 5 - 50 - ----MHz
Power Dissipation Capacitance
(Notes 4, 5)
C
PD
- 5-25-----pF
HCT TYPES
Propagation Delay,
CP to Q, Q (Figure 4)
t
PLH
, t
PHL
C
L
= 50pF 4.5 - - 35 - 44 - 53 ns
Propagation Delay,
R, S to Q, Q (Figure 4)
t
PHL
, t
PLH
CL = 50pF 4.5 - - 40 - 50 - 60 ns
Transition Time (Figure 4) t
TLH
, t
THL
C
L
= 50pF 4.5 - - 15 - 19 - 22 ns
Input Capacitance C
I
- - - - 10 - 10 - 10 pF
CP Frequency f
MAX
CL = 15pF 5 - 50 - ----MHz
Power Dissipation Capacitance
(Notes 4, 5)
C
PD
- 5-30-----pF
NOTES:
4. C
PD
is used to determine the dynamic power consumption, per flip-flop.
5. P
D
=C
PD
V
CC
2
f
i
+ Σ (C
L
V
CC
2
f
o
) where f
i
= input frequency, f
o
= output frequency, C
L
= output load capacitance, V
CC
= supply voltage.
Switching Specifications Input t
r
, t
f
= 6ns (Continued)
PARAMETER SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C -40
o
C TO 85
o
C -55
o
C TO 125
o
C
UNITSMIN TYP MAX MIN MAX MIN MAX
Test Circuits and Waveforms
NOTE: Outputs should be switching from 10% V
CC
to 90% V
CC
in
accordance with device truth table. For f
MAX
, input duty cycle = 50%.
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
NOTE: Outputs should be switching from 10% V
CC
to 90% V
CC
in
accordance with device truth table. For f
MAX
, input duty cycle = 50%.
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
CLOCK
90%
50%
10%
GND
V
CC
t
r
C
L
t
f
C
L
50%
50%
t
WL
t
WH
10%
t
WL
+ t
WH
=
f
CL
I
CLOCK
2.7V
1.3V
0.3V
GND
3V
t
r
C
L
= 6ns
t
f
C
L
= 6ns
1.3V
1.3V
t
WL
t
WH
0.3V
t
WL
+ t
WH
=
fC
L
I
t
PHL
t
PLH
t
THL
t
TLH
90%
50%
10%
50%
10%
INVERTING
OUTPUT
INPUT
GND
V
CC
t
r
= 6ns t
f
= 6ns
90%
t
PHL
t
PLH
t
THL
t
TLH
2.7V
1.3V
0.3V
1.3V
10%
INVERTING
OUTPUT
INPUT
GND
3V
t
r
= 6ns
t
f
= 6ns
90%
CD54HC74, CD74HC74, CD54HCT74, CD74HCT74