Datasheet

5
HCT TYPES
High Level Input
Voltage
V
IH
- - 4.5 to
5.5
2-- 2 - 2 - V
Low Level Input
Voltage
V
IL
- - 4.5 to
5.5
- - 0.8 - 0.8 - 0.8 V
High Level Output
Voltage
CMOS Loads
V
OH
V
IH
or V
IL
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
High Level Output
Voltage
TTL Loads
-4 4.5 3.98 - - 3.84 - 3.7 - V
Low Level Output
Voltage
CMOS Loads
V
OL
V
IH
or V
IL
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage
TTL Loads
4 4.5 - - 0.26 - 0.33 - 0.4 V
Input Leakage
Current
I
I
V
CC
and
GND
05.5--±0.1 - ±1-±1 μA
Quiescent Device
Current
I
CC
V
CC
or
GND
0 5.5 - - 8 - 80 - 160 μA
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
ΔI
CC
(Note 2)
V
CC
-2.1
- 4.5 to
5.5
- 100 360 - 450 - 490 μA
NOTE:
2. For dual-supply systems theoretical worst case (V
I
= 2.4V, V
CC
= 5.5V) specification is 1.8mA.
DC Electrical Specifications (Continued)
PARAMETER SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C-40
o
C TO 85
o
C-55
o
C TO 125
o
C
UNITSV
I
(V) I
O
(mA) MIN TYP MAX MIN MAX MIN MAX
HCT Input Loading Table
INPUT UNIT LOADS
Enable 0.7
Data Inputs 0.35
NOTE: Unit Load is ΔI
CC
limit specified in DC Electrical Table, e.g.,
360μA max at 25
o
C.
Switching Specifications Input t
r
, t
f
= 6ns
PARAMETER SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C-40
o
C TO 85
o
C-55
o
C TO 125
o
C
UNITSMIN TYP MAX MIN MAX MIN MAX
HC TYPES
Propagation Delay (Figure 1) t
PLH,
t
PHL
C
L
= 50pF 2 - - 170 - 210 - 255 ns
An to Output 4.5 - - 34 - 42 - 51 ns
C
L
=15pF 5 - 14 - - - - - ns
C
L
= 50pF 6 - - 29 - 36 - 43 ns
Bn to Output t
PLH,
t
PHL
C
L
= 50pF 2 - - 170 - 210 - 255 ns
4.5 - - 34 - 42 - 51 ns
C
L
=15pF 5 - 14 - - - - - ns
C
L
= 50pF 6 - - 29 - 36 - 43 ns
CD54HC688, CD74HC688, CD54HCT688, CD74HCT688