Datasheet

9
Timing Diagram
SHIFT CLOCK
SH
CP
SERIAL DATE
D
S
MASTER RESET
MR
PARALLEL LOAD
PL
STORAGE CLOCK
ST
CP
D0
D1
D2
D3
D4
D5
D6
D7
Q7
PARALLEL
DATA
INPUTS
RESET
SHIFT
REGISTER
SERIAL
SHIFT
L
H
H
H
H
H
HHHH H H H HH
L
L
LL L L L L LLL L
L
L
L
L
L
L
L
H
L
L
L
L
H
H
L
H
LOAD
FLIP-FLOPS
LOAD
FLIP-FLOPS
PARALLEL LOAD
SHIFT REGISTER
PARALLEL LOAD
SHIFT REGISTER
PARALLEL LOAD FLIP-FLOP
S
AND SHIFT REGISTER
SERIAL
SHIFT
SERIAL
SHIFT
SERIAL
SHIFT
CD54HC597, CD74HC597, CD74HCT597