Datasheet

5
Low Level Output
Voltage
CMOS Loads
V
OL
V
IH
or V
IL
0.02 2 - - 0.1 - 0.1 - 0.1 V
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
0.02 6 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage
TTL Loads
- - ---- - - - V
4 4.5 - - 0.26 - 0.33 - 0.4 V
5.2 6 - - 0.26 - 0.33 - 0.4 V
Input Leakage
Current A,
B, R
I
I
V
CC
or
GND
-6--±0.1 - ±1-±1 µA
Input Leakage
Current R
X
C
X
(Note 6)
-6--±0.05 - ±0.5 - ±0.5 µA
Quiescent Device
Current
I
CC
V
CC
or
GND
0 6 - - 8 - 80 - 160 µA
Active Device Current
Q = High & Pins 2, 14
at V
CC
/4
I
CC
V
CC
or
GND
0 6 - - 0.6 - 0.8 - 1 mA
HCT TYPES
High Level Input
Voltage
V
IH
- - 4.5 to
5.5
2-- 2 - 2 - V
Low Level Input
Voltage
V
IL
- - 4.5 to
5.5
- - 0.8 - 0.8 - 0.8 V
High Level Output
Voltage
CMOS Loads
V
OH
V
IH
or V
IL
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
High Level Output
Voltage
TTL Loads
-4 4.5 3.98 - - 3.84 - 3.7 - V
Low Level Output
Voltage
CMOS Loads
V
OL
V
IH
or V
IL
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage
TTL Loads
4 4.5 - - 0.26 - 0.33 - 0.4 V
Input Leakage
Current
I
I
V
CC
and
GND
- 5.5 - ±0.1 - ±1-±1 µA
Input Leakage
Current R
X
C
X
(Note 6)
- 5.5 - - ±0.05 - ±0.5 - ±0.5 µA
Quiescent Device
Current
I
CC
V
CC
or
GND
0 5.5 - - 8 - 80 - 160 µA
Active Device Current
Q = High & Pins 2, 14
at V
CC
/4
I
CC
V
CC
or
GND
0 5.5 - - 0.6 - 0.8 - 1 mA
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I
CC
(Note 7)
V
CC
-2.1
- 4.5 to
5.5
- 100 360 - 450 - 490 µA
NOTES:
6. When testing I
IL
the Q output must be high. If Q is low (device not triggered) the pull-up P device will be ON and the low resistance path
from V
DD
to the test pin will cause a current far exceeding the specification.
7. For dual-supply systems theoretical worst case (V
I
= 2.4V, V
CC
= 5.5V) specification is 1.8mA.
DC Electrical Specifications (Continued)
PARAMETER SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C -40
o
C TO 85
o
C -55
o
C TO 125
o
C
UNITSV
I
(V) I
O
(mA) MIN TYP MAX MIN MAX MIN MAX
CD54HC4538, CD74HC4538, CD54HCT4538, CD74HCT4538