Datasheet

14
Test Circuits and Waveforms
NOTE: Outputs should be switching from 10% V
CC
to 90% V
CC
in
accordance with device truth table. For f
MAX
, input duty cycle = 50%.
FIGURE 15. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
NOTE: Outputs should be switching from 10% V
CC
to 90% V
CC
in
accordance with device truth table. For f
MAX
, input duty cycle = 50%.
FIGURE 16. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
FIGURE 17. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
FIGURE 18. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
FIGURE 19. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 20. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
CLOCK
90%
50%
10%
GND
V
CC
t
r
C
L
t
f
C
L
50%
50%
t
WL
t
WH
10%
t
WL
+ t
WH
=
fC
L
I
CLOCK
2.7V
1.3V
0.3V
GND
3V
t
r
C
L
= 6ns
t
f
C
L
= 6ns
1.3V
1.3V
t
WL
t
WH
0.3V
t
WL
+ t
WH
=
fC
L
I
t
PHL
t
PLH
t
THL
t
TLH
90%
50%
10%
50%
10%
INVERTING
OUTPUT
INPUT
GND
V
CC
t
r
= 6ns t
f
= 6ns
90%
t
PHL
t
PLH
t
THL
t
TLH
2.7V
1.3V
0.3V
1.3V
10%
INVERTING
OUTPUT
INPUT
GND
3V
t
r
= 6ns
t
f
= 6ns
90%
t
r
C
L
t
f
C
L
GND
V
CC
GND
V
CC
50%
90%
10%
GND
CLOCK
INPUT
DATA
INPUT
OUTPUT
SET, RESET
OR PRESET
V
CC
50%
50%
90%
10%
50%
90%
t
REM
t
PLH
t
SU(H)
t
TLH
t
THL
t
H(L)
t
PHL
IC
C
L
50pF
t
SU(L)
t
H(H)
t
r
C
L
t
f
C
L
GND
3V
GND
3V
1.3V
2.7V
0.3V
GND
CLOCK
INPUT
DATA
INPUT
OUTPUT
SET, RESET
OR PRESET
3V
1.3V
1.3V
1.3V
90%
10%
1.3V
90%
t
REM
t
PLH
t
SU(H)
t
TLH
t
THL
t
H(L)
t
PHL
IC
C
L
50pF
t
SU(L)
1.3V
t
H(H)
1.3V
CD54HC4351, CD74HC4351, CD74HCT4351, CD74HC4352