Datasheet

7
HCT TYPES
Propagation Delay Time
(Figure 2)
t
PLH,
t
PHL
C
L
= 50pF 4.5 - - 40 - 50 - 60 ns
CP to Q1’ Output C
L
=15pF 5 - 17 - - - - - ns
Q
n
to Q
n
+ 1 t
PLH,
t
PHL
C
L
= 50pF 4.5 - - 15 - 19 - 22 ns
C
L
=15pF 5 - 6 - - - - - ns
MR to Q
n
t
PLH,
t
PHL
C
L
= 50pF 4.5 - - 40 - 50 - 60 ns
C
L
=15pF 5 - 17 - - - - - ns
Output Transition t
TLH
,t
THL
C
L
= 50pF 4.5 - - 15 - 19 - 22 ns
Input Capacitance C
IN
C
L
=15pF - - - 10 - 10 - 10 pF
Power Dissipation Capaci-
tance
(Notes 3, 4)
C
PD
C
L
=15pF 5 - 30 - - - - - pF
NOTES:
3. C
PD
is used to determine the dynamic power consumption, per package.
4. P
D
= V
CC
2
f
i
(C
PD
+ C
L
) where f
i
= Input Frequency, C
L
= Output Load Capacitance, V
CC
= Supply Voltage.
Switching Specifications Input t
r
, t
f
= 6ns (Continued)
PARAMETER SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C -40
o
C TO 85
o
C -55
o
C TO 125
o
C
UNITSMIN TYP MAX MIN MAX MIN MAX
Test Circuits and Waveforms
NOTE: Outputs should be switching from 10% V
CC
to 90% V
CC
in
accordance with device truth table. For f
MAX
, input duty cycle = 50%.
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
NOTE: Outputs should be switching from 10% V
CC
to 90% V
CC
in
accordance with device truth table. For f
MAX
, input duty cycle = 50%.
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
CLOCK
90%
50%
10%
GND
V
CC
t
r
C
L
t
f
C
L
50%
50%
t
WL
t
WH
10%
t
WL
+ t
WH
=
f
CL
I
CLOCK
2.7V
1.3V
0.3V
GND
3V
t
r
C
L
= 6ns
t
f
C
L
= 6ns
1.3V
1.3V
t
WL
t
WH
0.3V
t
WL
+ t
WH
=
fC
L
I
CD54HC4020, CD74HC4020, CD54HCT4020, CD74HCT4020