Datasheet

6
FIGURE 3. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED
SEQUENTIAL LOGIC CIRCUITS
Timing Diagrams
FIGURE 4. FIGURE 5.
Test Circuits and Waveforms (Continued)
t
r
C
L
t
f
C
L
GND
V
CC
GND
V
CC
50%
90%
10%
GND
CLOCK
INPUT
DATA
INPUT
OUTPUT
SET, RESET
OR PRESET
V
CC
50%
50%
90%
10%
50%
90%
t
REM
t
PLH
t
SU(H)
t
TLH
t
THL
t
H(L)
t
PHL
IC
C
L
50pF
t
SU(L)
t
H(H)
C
L
C
L
P
N
P
N
PN
P
N
D
C
L
Q
C
FF DETAIL
C
L
C
L
C
L
C
L
C
L
C
L
Q
R
CLOCK
MASTER
RESET
CLOCK
ENABLE
“0”
“1”
“2”
“3”
“4”
“5”
“6”
“7”
“8”
“9”
TERMINAL
COUNT
0
1
2
3
4
5
6
7
8
9
0
1
2
CD54HC4017, CD74HC4017