Datasheet

5
MR to any Dec. Out t
PLH,
t
PHL
C
L
= 50pF 2 - - 230 - 290 - 345 ns
C
L
= 50pF 4.5 - - 46 - 58 - 69 ns
C
L
= 15pF 5 - 19 - - - - - ns
C
L
= 50pF 6 - - 39 - 49 - 59 ns
MR to TC t
PLH,
t
PHL
C
L
= 50pF 2 - - 230 - 290 - 345 ns
C
L
= 50pF 4.5 - - 46 - 58 - 69 ns
C
L
= 15pF 5 - 19 - - - - - ns
C
L
= 50pF 6 - - 39 - 49 - 59 ns
Transition Time TC, Dec. Out t
TLH
,t
THL
C
L
= 50pF 2 - - 75 - 95 - 110 ns
C
L
= 50pF 4.5 - - 15 - 19 - 22 ns
C
L
= 50pF 6 - - 13 - 16 - 19 ns
Input Capacitance C
IN
C
L
= 50pF - - - 10 - 10 - 10 pF
Maximum CP Frequency f
MAX
C
L
= 15pF 5 - 60 - - - - - MHz
Power Dissipation Capacitance
(Notes 2, 3)
C
PD
C
L
= 15pF 5 - 39 - - - - - pF
NOTES:
2. C
PD
is used to determine the dynamic power consumption, per package.
3. P
D
= V
CC
2
f
i
Σ€ C
L
V
CC
2
fo where f
i
= input frequency, f
o
= output frequency, C
L
= output load capacitance, V
CC
= supply voltage.
Switching Specifications Input t
r
, t
f
= 6ns (Continued)
PARAMETER SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO
85
o
C -55
o
C TO 125
o
C
UNITSMIN TYP MAX MIN MAX MIN MAX
Test Circuits and Waveforms
NOTE: Outputs should be switching from 10% V
CC
to 90% V
CC
in
accordance with device truth table. For f
MAX
, input duty cycle = 50%.
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
FIGURE 2. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
CLOCK
90%
50%
10%
GND
V
CC
t
r
C
L
t
f
C
L
50%
50%
t
WL
t
WH
10%
t
WL
+ t
WH
=
fC
L
I
t
PHL
t
PLH
t
THL
t
TLH
90%
50%
10%
50%
10%
INVERTING
OUTPUT
INPUT
GND
V
CC
t
r
= 6ns t
f
= 6ns
90%
CD54HC4017, CD74HC4017