Datasheet

5
Test Circuit and Waveform
FIGURE 1. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED
SEQUENTIAL LOGIC CIRCUITS
t
r
C
L
t
f
C
L
GND
V
CC
GND
V
CC
50%
90%
10%
GND
CLOCK
INPUT
DATA
INPUT
OUTPUT
SET, RESET
OR PRESET
V
CC
50%
50%
90%
10%
50%
90%
t
REM
t
PLH
t
SU(H)
t
TLH
t
THL
t
H(L)
t
PHL
IC
C
L
50pF
t
SU(L)
t
H(H)
CD54HC4015, CD74HC4015