Datasheet

11
FIGURE 7. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 8. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 9. HC THREE-STATE PROPAGATION DELAY
WAVEFORM
FIGURE 10. HCT THREE-STATE PROPAGATION DELAY
WAVEFORM
NOTE: Open drain waveforms t
PLZ
and t
PZL
are the same as those for three-state shown on the left. The test circuit is Output R
L
=1kΩ to
V
CC
, C
L
= 50pF.
FIGURE 11. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT
Test Circuits and Waveforms (Continued)
t
r
C
L
t
f
C
L
GND
V
CC
GND
V
CC
50%
90%
10%
GND
CLOCK
INPUT
DATA
INPUT
OUTPUT
SET, RESET
OR PRESET
V
CC
50%
50%
90%
10%
50%
90%
t
REM
t
PLH
t
SU(H)
t
TLH
t
THL
t
H(L)
t
PHL
IC
C
L
50pF
t
SU(L)
t
H(H)
t
r
C
L
t
f
C
L
GND
3V
GND
3V
1.3V
2.7V
0.3V
GND
CLOCK
INPUT
DATA
INPUT
OUTPUT
SET, RESET
OR PRESET
3V
1.3V
1.3V
1.3V
90%
10%
1.3V
90%
t
REM
t
PLH
t
SU(H)
t
TLH
t
THL
t
H(L)
t
PHL
IC
C
L
50pF
t
SU(L)
1.3V
t
H(H)
1.3V
50%
10%
90%
GN
D
V
CC
10%
90%
50%
50%
OUTPUT
DISABLE
OUTPUT LOW
TO OFF
O
UTPUT HIGH
TO OFF
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
6ns 6ns
t
PZH
t
PHZ
t
PZL
t
PLZ
0.3
2.7
GN
D
3V
10%
90%
1.3V
1.3V
OUTPUT
DISABLE
OUTPUT LOW
TO OFF
O
UTPUT HIGH
TO OFF
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
t
r
6ns
t
PZH
t
PHZ
t
PZL
t
PLZ
6ns t
f
1.3
IC WITH
THREE-
STATE
OUTPUT
OTHER
INPUTS
T
IED HIGH
OR LOW
OUTPUT
DISABLE
V
CC
FOR t
PLZ
AND t
PZL
GND FOR t
PHZ
AND t
PZ
H
OUTPUT
R
L
= 1kΩ
C
L
50pF
CD54HC40105, CD74HC40105, CD54HCT40105, CD74HCT40105