Datasheet

8
Test Circuits and Waveforms
FIGURE 2. FIGURE 3.
FIGURE 4. FIGURE 5.
FIGURE 6. FIGURE 7.
NOTE: Outputs should be switching from 10% V
CC
to 90% V
CC
in
accordance with device truth table. For f
MAX
, input duty cycle = 50%.
FIGURE 8. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
NOTE: Outputs should be switching from 10% V
CC
to 90% V
CC
in
accordance with device truth table. For f
MAX
, input duty cycle = 50%.
FIGURE 9. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
t
r
CP
TC
t
THL
t
PHL
t
W
90%
10%
t
f
V
S
GND
t
PLH
t
TLH
INPUT LEVEL
1/f
MAX
V
S
90%
10%
INPUT LEVEL
GND
V
S
MR
CP
t
REM
t
W
V
S
GND
INPUT LEVEL
t
f
10%
90%
TE
t
PHL
TC
t
THL
t
TLH
V
S
t
PLH
V
S
t
f
INPUT LEVEL
10%
90%
MR
CP
V
S
t
SU
V
S
t
h
INPUT LEVEL
GND
INPUT LEVEL
GND
INPUTS
P0 - P7
PE
CP
V
S
V
S
VALID
t
SU
t
h
V
S
t
REC
INPUT LEVEL
GND
INPUT LEVEL
GND
INPUT LEVEL
GND
t
h
t
SU
TE
OR
PE
CP
V
S
t
SU
V
S
t
h
INPUT LEVEL
GND
INPUT LEVEL
GND
CLOCK
90%
50%
10%
GND
V
CC
t
r
C
L
t
f
C
L
50%
50%
t
WL
t
WH
10%
t
WL
+ t
WH
=
fC
L
I
CLOCK
2.7V
1.3V
0.3V
GND
3V
t
r
C
L
= 6ns
t
f
C
L
= 6ns
1.3V
1.3V
t
WL
t
WH
0.3V
t
WL
+ t
WH
=
fC
L
I
CD54HC40103, CD74HC40103, CD74HCT40103