Datasheet

7
HCT TYPES
Propagation Delay t
PHL,
t
PLH
Clock to I/O Output,
Clock to Q0 and Q7
C
L
= 50pF 4.5 - - 45 - 56 - 68 ns
C
L
= 15pF 5 - 19 - - - - - ns
MR to Output t
PHL,
t
PLH
C
L
= 50pF 4.5 - - 46 - 58 - 69 ns
Output Enable and Disable
Times
t
PZL
,t
PZH
,
t
PLZ
, t
PHZ
C
L
= 15pF 5 - 10,
13, 15
--- - -ns
Output High-Z to High Level t
PZH
C
L
= 50pF 4.5 - - 32 - 40 - 48 ns
Output High Level to High-Z t
PHZ
C
L
= 50pF 4.5 - - 37 - 46 - 56 ns
Output Low Level to High-Z t
PLZ
C
L
= 50pF 4.5 - - 32 - 40 - 48 ns
Output High-Z to Low Level t
PZL
C
L
= 50pF 4.5 - - 30 - 38 - 45 ns
Output Transition Time t
TLH
, t
THL
Q0, Q7 C
L
= 50pF 4.5 - - 15 - 19 - 22 ns
I/O
0
to I/O
7
C
L
= 50pF 4.5 - - 12 - 15 - 18 ns
Input Capacitance C
IN
C
L
= 50pF - 10 - 10 - 10 - 10 pF
Three-State Output
Capacitance
C
O
- - 20 - 20 - 20 - 20 pF
Power Dissipation Capacitance
(Notes 3, 4)
C
PD
C
L
= 15pF 5 - 170 - - - - - pF
NOTES:
3. C
PD
is used to determine the dynamic power consumption, per register.
4. P
D
=C
PD
V
CC
2
f
i
+ ∑ (C
L
V
CC
2
f
O
) where f
i
= Input Frequency, f
O
= Output Frequency, C
L
= Output Load Capacitance,
V
CC
= Supply Voltage.
Switching Specifications C
L
= 50pF, Input t
r
, t
f
= 6ns (Continued)
PARAMETER SYMBOL
TEST
CONDITIONS V
CC
(V)
25
o
C
-40
o
C TO
85
o
C
-55
o
C TO
125
o
C
UNITSMIN TYP MAX MIN MAX MIN MAX
Test Circuits and Waveforms
NOTE: Outputs should be switching from 10% V
CC
to 90% V
CC
in
accordance with device truth table. For f
MAX
, input duty cycle = 50%.
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
NOTE: Outputs should be switching from 10% V
CC
to 90% V
CC
in
accordance with device truth table. For f
MAX
, input duty cycle = 50%.
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
CLOCK
90%
50%
10%
GND
V
CC
t
r
C
L
t
f
C
L
50%
50%
t
WL
t
WH
10%
t
WL
+ t
WH
=
fC
L
I
CLOCK
2.7V
1.3V
0.3V
GND
3V
t
r
C
L
= 6ns
t
f
C
L
= 6ns
1.3V
1.3V
t
WL
t
WH
0.3V
t
WL
+ t
WH
=
fC
L
I
CD54HC299, CD74HC299, CD54HCT299, CD74HCT299