Datasheet

6
Power Dissipation
Capacitance
(Notes 3, 4)
C
PD
- 5 25 - - - pF
HCT TYPES
Propagation Delay,
Clock to Output (Figure 4)
t
PLH
, t
PHL
C
L
= 50pF 4.5 - 30 38 45 ns
C
L
= 15pF 5 12 - - - ns
Propagation Delay,
MR to Output (Figure 4)
t
PHL
C
L
= 50pF 4.5 - 32 40 48 ns
Output Transition Time t
TLH
, t
THL
C
L
= 50pF 4.5 - 15 19 22 ns
Input Capacitance C
IN
---1010 10pF
Maximum Clock Frequency f
MAX
C
L
= 15pF 5 50 - - - MHz
Power Dissipation
Capacitance
(Notes 3, 4)
C
PD
- 5 25 - - - pF
NOTES:
3. C
PD
is used to determine the dynamic power consumption, per flip-flop.
4. P
D
=C
PD
V
CC
2
f
i
+ ∑ (C
L
V
CC
2
+f
O
) where f
i
= Input Frequency, f
O
= Output Frequency, C
L
= Output Load Capacitance, V
CC
= Supply
Voltage.
Switching Specifications Input t
r
, t
f
= 6ns (Continued)
PARAMETER SYMBOL
TEST
CONDITIONS V
CC
(V)
25
o
C -40
o
C TO 85
o
C
-55
o
C TO
125
o
C
UNITSTYP MAX MAX MAX
Test Circuits and Waveforms
NOTE: Outputs should be switching from 10% V
CC
to 90% V
CC
in
accordance with device truth table. For f
MAX
, input duty cycle = 50%.
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
NOTE: Outputs should be switching from 10% V
CC
to 90% V
CC
in
accordance with device truth table. For f
MAX
, input duty cycle = 50%.
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
CLOCK
90%
50%
10%
GND
V
CC
t
r
C
L
t
f
C
L
50%
50%
t
WL
t
WH
10%
t
WL
+ t
WH
=
fC
L
I
CLOCK
2.7V
1.3V
0.3V
GND
3V
t
r
C
L
= 6ns
t
f
C
L
= 6ns
1.3V
1.3V
t
WL
t
WH
0.3V
t
WL
+ t
WH
=
fC
L
I
t
PHL
t
PLH
t
THL
t
TLH
90%
50%
10%
50%
10%
INVERTING
OUTPUT
INPUT
GND
V
CC
t
r
= 6ns t
f
= 6ns
90%
t
PHL
t
PLH
t
THL
t
TLH
2.7V
1.3V
0.3V
1.3V
10%
INVERTING
OUTPUT
INPUT
GND
3V
t
r
= 6ns
t
f
= 6ns
90%
CD54/74HC273, CD54/74HCT273