Datasheet

2
Pinout
CD54HC259, CD54HCT259
(CERDIP)
CD74HC259, CD74HCT259
(PDIP, SOIC)
TOP VIEW
Functional Diagram
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
A0
A1
A2
Q0
Q1
Q2
GND
Q3
V
CC
LE
D
Q7
Q6
Q5
Q4
MR
1
2
3
14
15
13
4
5
6
7
10
12
11
9
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
MR
LE
8
LATCHES
1-OF-8
DECODER
D
A
2
A
1
A
0
GND = 8
V
CC
= 16
TRUTH TABLE
INPUTS OUTPUT OF
ADDRESS
LATCH
EACH OTHER
OUTPUT FUNCTIONMR LE
HL D Q
io
Addressable
Latch
HH Q
io
Q
io
Memory
L L D L 8-Line
Demultiplexer
L H L L Reset
H = High Voltage Level
L = Low Voltage Level
D = The level at the data input
Q
io
= The level of Q
i
(i = 0, 1...7, as appropriate) before the indicat-
ed steady-state input conditions were established.
LATCH SELECTION TABLE
SELECT INPUTS
LATCH
ADDRESSEDA2 A1 A0
LLL 0
LLH 1
LHL 2
LHH 3
HLL 4
HLH 5
HHL 6
HHH 7
CD54HC259, CD74HC259, CD54HCT259, CD74HCT259