Datasheet

6
Output Enable and Disable
Times
t
TLH,
t
THL
C
L
= 50pF 4.5 - - 30 - - 38 - - 45 ns
Output Transition Time t
THL
, t
TLH
C
L
= 50pF 4.5 - - 12 - - 15 - - 18 ns
Input Capacitance C
I
C
L
= 50pF - 10 - 10 - - 10 - - 10 pF
Power Dissipation Capacitance
(Notes 3, 4)
C
PD
HCT240 - 5 - 40 - - - ----pF
HCT241 - 5 - 38 - - - ----pF
HCT244 - 5 - 40 - - - ----pF
NOTES:
3. C
PD
is used to determine the dynamic power consumption, per channel.
4. P
D
= V
CC
2
f
i
(C
PD
+ C
L
) where f
i
= Input Frequency, f
O
= Output Frequency, C
L
= Output Load Capacitance, V
CC
= Supply Voltage.
Test Circuits and Waveforms
FIGURE 1. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
FIGURE 3. HC THREE-STATE PROPAGATION DELAY
WAVEFORM
FIGURE 4. HCT THREE-STATE PROPAGATION DELAY
WAVEFORM
Switching Specifications C
L
= 50pF, Input t
r
, t
f
= 6ns (Continued)
PARAMETER SYMBOL
TEST
CONDI-
TIONS
V
CC
(V)
25
o
C -40
o
C TO 85
o
C -55
o
C TO 125
o
C
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
t
PHL
t
PLH
t
THL
t
TLH
90%
50%
10%
50%
10%
INVERTING
OUTPUT
INPUT
GND
V
CC
t
r
= 6ns t
f
= 6ns
90%
t
PHL
t
PLH
t
THL
t
TLH
2.7V
1.3V
0.3V
1.3V
10%
INVERTING
OUTPUT
INPUT
GND
3V
t
r
= 6ns
t
f
= 6ns
90%
50%
10%
90%
GN
D
V
CC
10%
90%
50%
50%
OUTPUT
DISABLE
OUTPUT LOW
TO OFF
O
UTPUT HIGH
TO OFF
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
6ns 6ns
t
PZH
t
PHZ
t
PZL
t
PLZ
0.3
2.7
GN
D
3V
10%
90%
1.3V
1.3V
OUTPUT
DISABLE
OUTPUT LOW
TO OFF
O
UTPUT HIGH
TO OFF
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
t
r
6ns
t
PZH
t
PHZ
t
PZL
t
PLZ
6ns t
f
1.3
CD54/74HC240, CD54/74HCT240, CD74HC241, CD54/74HCT241, CD54/74HC244, CD54/74HCT244