Datasheet

5
Test Circuit and Waveforms
FIGURE 1. CLOCK PREREQUISITE AND PROPAGATION
DELAYS AND OUTPUT TRANSITION TIMES
FIGURE 2. MASTER RESET PREREQUISITE AND
PROPAGATION DELAYS
FIGURE 3. J, K, OR PARALLEL ENABLE PREREQUISITE TIMES
CLOCK
Q OR
Q
V
CC
GND
t
THL
t
TLH
10%
90%
l/f
MAX
t
W
t
r
t
f
V
S
t
PLH
t
PHL
10%
90%
0.5 V
CC
RESET
Q
t
PLH
Q
CLOCK
t
REM
V
S
t
PHL
V
S
t
W
V
CC
GND
V
CC
GND
0.5 V
CC
0.5 V
CC
PE, K
VALID
J
0.5 V
CC
t
SU
CLOCK
V
S
V
CC
GND
GND
t
h
CD54HC195, CD74HC195