Datasheet

7
Test Circuits and Waveforms
FIGURE 1. CLOCK PREREQUISITE TIMES AND
PROPAGATION AND OUTPUT TRANSITION TIMES
FIGURE 2. MASTER RESET PREREQUISITE TIMES AND
PROPAGATION DELAYS
FIGURE 3. DATA PREREQUISITE TIMES FIGURE 4. PARALLEL LOAD OR SHIFT-LEFT/SHIFT-RIGHT
PREREQUISITE TIMES
I
NPUT LEVEL
CP
t
r
V
S
Q
t
THL
t
TLH
10%
90%
GN
D
V
S
V
S
90%
t
PHL
t
W
V
S
10%
10%
t
f
t
PLH
V
S
MR
V
S
V
S
INPUT LEVEL
GND
t
REM
V
S
INPUT LEVEL
GND
CP
Q
t
PHL
V
S
t
W
DATA
CP
t
SU
V
S
VALID
t
H
V
S
INPUT LEVEL
INPUT LEVEL
GND
GND
VALID
S OR DS
V
S
t
SU
t
H
V
S
CP
INPUT LEVEL
GND
INPUT LEVEL
GND