Datasheet

2
Functional Diagram
Logic Diagram
TRUTH TABLE
INPUTS OUTPUTS
RESET (MR) CLOCK CP DATA D
n
Q
n
Q
n
LXXLH
H ↑ HHL
H ↑ LLH
HLXQ
0
Q
0
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, ↑ = Transition from Low to High Level,
Q
0
= Level Before the Indicated Steady-State Input Conditions Were Established.
CP
D
R
2
Q
0
9
4
D
0
CP
Q
Q
3
Q
0
MR
1
CP
D
R
7
Q
1
5
D
1
Q
Q
6
Q
1
CP
D
R
10
Q
2
12
D
2
Q
Q
11
Q
2
CP
D
R
15
Q
3
13
D
3
Q
Q
14
Q
3
C
L
p
n
C
L
D
n
MR
CP
1
9
4 (5, 12, 13) D
C
L
C
L
C
L
C
L
TO OTHER THREE F/F
TO OTHER THREE F/F
R
Q
n
2( 7, 10, 15)
CP
C
L
p
n
C
L
p
n
C
L
C
L
p
n
816
V
CC
ONE OF FOUR F/F
Q
n
GND
3( 6, 11, 14)
CD54HC175, CD74HC175, CD54HCT175, CD74HCT175