Datasheet

2
Functional Diagram
Logic Diagram
TRUTH TABLE
INPUTS OUTPUT
RESET (MR) CLOCK CP DATA D
n
Q
n
LXXL
H ↑ HH
H ↑ LL
HLXQ
0
H = High Voltage Level, L = Low Voltage Level, X = Irrelevant, ↑ = Transition from Low to
High Level, Q
0
= Level Before the Indicated Steady-State Input Conditions Were Established
CP
D
R
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
D
0
CP
D
1
D
2
D
3
D
4
D
5
MR
C
L
p
n
C
L
D
n
MR
CP
1
9
3 (4, 6, 11, 13, 14) D
C
L
C
L
C
L
C
L
TO OTHER FIVE F/F
TO OTHER FIVE F/F
R
Q
n
2 (5, 7, 10, 12, 15
)
Q
CP
C
L
p
n
C
L
p
n
C
L
C
L
p
n
816
V
CC
ONE OF SIX F/F
CD54HC174, CD74HC174, CD54HCT174, CD74HCT174