Datasheet

7
Test Circuits and Waveforms
FIGURE 3. SERIAL-SHIFT MODE FIGURE 4. PARALLEL-LOAD MODE
FIGURE 5. PARALLEL-LOAD MODE FIGURE 6. PARALLEL-LOAD MODE
FIGURE 7. SERIAL-SHIFT MODE FIGURE 8. SERIAL-SHIFT MODE
FIGURE 9. SERIAL-SHIFT, CLOCK-INHIBIT MODE
CP OR CE
90%
10%
t
r
t
f
t
W
t
PHL
t
PLH
Q
7
OR Q
7
t
TLH
t
THL
1/f
MAX
GND
90%
10%
V
S
V
S
PL
t
W
t
PLH
t
PHL
Q
7
OR Q
7
INPUT LEVEL
V
S
V
S
t
r
t
f
INPUT D7
t
PLH
Q
7
OR Q
7
t
TLH
V
S
GND
INPUT LEVEL
t
THL
t
PHL
90%
10%
90%
10%
VALID
INPUTS D0-D7
t
SU
PL
V
S
t
H
GND
INPUT LEVEL
INPUT LEVEL
GND
V
S
VALID
INPUTS DS
CP OR
CE
GND
GND
INPUT LEVEL
t
H
t
SU
INPUT LEVEL
PL
V
S
t
REC
CP OR CE
V
S
INPUT LEVEL
GND
INPUT LEVEL
GND
CE INHIBITED
CP
t
SU
CE
INHIBITED
GND
INPUT LEVEL
INPUT LEVEL
GND
t
SU
(L) t
SU
CP
t
SU
(L)
CD54HC165, CD74HC165, CD54HCT165, CD74HCT165