Datasheet

2
Functional Diagram
TRUTH TABLE
OPERATING MODE
INPUTS Q
n
REGISTER OUTPUTS
PL CE CP DS D0 - D7 Q
0
Q
1
- Q
6
Q
7
Q
7
Parallel Load L X X X L L L-L L H
LXXXHHH-HHL
Serial Shift H L ↑ lXLq
0 -
q
5
q
6
q
6
HL↑ hXHq
0 -
q
5
q
6
q
6
Hold Do Nothing H H X X X q
0
q
1 -
q
6
q
7
q
7
H =High Voltage Level
h = High Voltage Level One Set-up Time Prior To The Low-to-high Clock Transition
l = Low Voltage Level One Set-up Time Prior To The Low-to-high Clock Transition
L = Low Voltage Level
X = Don’t Care
↑ = Transition from Low to High Level
q
n
= Lower Case Letters Indicate The State Of the Reference Output Clock Transition
9
7
Q
7
Q
7
11
12
14
4
3
13
D5
D4
D3
D2
D1
D0
5
D6
6
D7
10
DS
CE
2
PL
DATA
INPUTS
SERIAL
OUTPUTS
CP
151
PARALLEL
GND = 8
VCC = 16
CD54HC165, CD74HC165, CD54HCT165, CD74HCT165