Datasheet
M54HC147
M74HC147
October 1992
10 TO 4 LINE PRIORITY ENCODER
B1R
(Plastic Package)
ORDER CODES :
M54HC147F1R M74HC147M1R
M74HC147B1R M74HC147C1R
F1R
(Ceramic Package)
M1R
(Micro Package)
C1R
(Chip Carrier)
PIN CONNECTIONS (top view)
NC =
No Internal
Connection
INPUT AND OUTPUT EQUIVALENT CIRCUIT
DESCRIPTION
.HIGH SPEED
t
PD
= 15 ns (TYP.) at V
CC
=5V
.LOW POWER DISSIPATION
I
CC
=4µA (MAX.) at T
A
=25°C
.HIGH NOISE IMMUNITY
V
NIH
=V
NIL
=28%V
CC
(MIN.)
.OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
.SYMMETRICAL OUTPUT IMPEDANCE
I
OH
=I
OL
= 4 mA (MIN.)
.BALANCED PROPAGATION DELAYS
t
PLH
=t
PHL
.WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR) = 2 V to 6 V
.PIN AND FUNCTION COMPATIBLE
WITH 54/74LS147
The M54/74HC147 is a high speed CMOS 10 TO 4
LINE PRIORITY ENCODER fabricated in silicon
gate C
2
MOS technology. It has the same high
speed performance of LSTTL combined with true
CMOS low power consumption.
This device features priority encoding of the inputs
to ensure that only the highest order data line is en-
coded. Nine input lines are encoded to a four line
BCD output. The implied decimal zero condition re-
quires no input condition as zero is encoded when
allnine datalinesare athigh logic level. Alldatainput
and outputs are active at the low logic level. All in-
puts are equipped with protection circuits against
static discharge and transient excess voltage.
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