Datasheet

5
Power Dissipation Capacitance
(Notes 5, 6)
C
PD
- 5-9-----pF
NOTES:
5. C
PD
is used to determine the dynamic power consumption, per gate.
6. P
D
= C
PD
V
CC
2
f
i
+ Σ (C
L
V
CC
2
f
o
) + Σ (V
L
2
/R
L
) (Duty Factor “Low”)
where f
i
= input frequency, f
o
= output frequency, C
L
= output load capacitance, V
CC
= supply voltage, Duty Factor “Low” = percent of
time output is “low”, V
L
= output voltage, R
L
= pull-up resistor.
Switching Specifications Input t
r
, t
f
= 6ns (Continued)
PARAMETER SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C -40
o
C TO 85
o
C -55
o
C TO 125
o
C
UNITSMIN TYP MAX MIN MAX MIN MAX
Test Circuits and Waveforms
FIGURE 1. TRANSITION TIMES, PROPAGATION DELAY
TIMES, AND TEST CIRCUIT
FIGURE 2. MINIMUM RESISTIVE LOAD vs LOAD VOLTAGE
FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
INPUT LEVEL
V
S
t
PZL
V
OH
OUTPUT
1kΩ
V
CC
50pF
V
OL
90%
10%
t
THL
OUTPUT
OPEN
DRAIN
NAND
GATE
V
CC
nB(nA)
OUTPUT
nY
t
PLZ
nA(nB)
V
S
LOW
OFF
LOW
R
L
V
L
V
O
V
CC
= 5V
±10%
HC/HCT03
V
L
R
L
R
ON
V
O
0.8V (HCT V
IL
MAX)
≤ 1.35V (HC V
IL
MAX)
R
ON
MAX =
65Ω AT 25
o
C
4mA
=
0.26V
800
700
600
500
400
300
200
100
012345678910
V
L
, LOAD VOLTAGE (V)
R
L
MIN, PULLUP RESISTOR (Ω)
HC
HCT
t
PHL
t
PLH
t
THL
t
TLH
90%
50%
10%
50%
10%
INVERTING
OUTPUT
INPUT
GND
V
CC
t
r
= 6ns t
f
= 6ns
90%
t
PHL
t
PLH
t
THL
t
TLH
2.7V
1.3V
0.3V
1.3V
10%
INVERTING
OUTPUT
INPUT
GND
3V
t
r
= 6ns
t
f
= 6ns
90%
CD54HC03, CD74HC03, CD54HCT03, CD74HCT03