Datasheet

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CD74FCT273

BiCMOS OCTAL D-TYPE FLIP-FLOP

WITH RESET

SCBS737A – JULY 2000 – REVISED JULY 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

BiCMOS Technology With Low Quiescent

Power

Buffered Inputs

Direct Clear Input

48-mA Output Sink Current

Output Voltage Swing Limited to 3.7 V

Controlled Output Edge Rates

Input/Output Isolation From V

SCR Latch-Up-Resistant BiCMOS Process

and Circuit Design

Applications Include:

– Buffer/Storage Registers

– Shift Registers

– Pattern Generators

Package Options Include Plastic

Small-Outline (M) Package and Standard

Plastic (E) DIP

description

The CD74FCT273 is a positive-edge-triggered, D-type flip-flop with a direct clear (CLR) input. This device uses

a small-geometry BiCMOS technology. The output stage is a combination of bipolar and CMOS transistors that

limits the output high level to two diode drops below V

. This resultant lowering of output swing (0 V to 3.7 V)

reduces power-bus ringing [a source of electromagnetic interference (EMI)] and minimizes V

bounce and

ground bounce and their effects during simultaneous output switching. The output configuration also enhances

switching speed and is capable of sinking 48 mA.

Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the

positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not

directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the

D input has no effect at the output. All eight flip-flops are controlled by a common clock (CLK) and a common

reset (CLR

). The outputs are placed in a low state when CLR is taken low, independent of the CLK.

The CD74FCT273 is characterized for operation from 0°C to 70°C.

FUNCTION TABLE

(each flip-flop)

INPUTS

OUTPUT

CLR

CLK D

OUTPUT

L X X L

H ↑ HH

H ↑ LL

H L X Q

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

E OR M PACKAGE

(TOP VIEW)

CLR

GND

CLK

Summary of content (10 pages)

PAGE 1
CD74FCT273 BiCMOS OCTAL D-TYPE FLIP-FLOP WITH RESET SCBS737A – JULY 2000 – REVISED JULY 2000 D D D D D D D D D D E OR M PACKAGE (TOP VIEW) BiCMOS Technology With Low Quiescent Power Buffered Inputs Direct Clear Input 48-mA Output Sink Current Output Voltage Swing Limited to 3.
PAGE 2
CD74FCT273 BiCMOS OCTAL D-TYPE FLIP-FLOP WITH RESET SCBS737A – JULY 2000 – REVISED JULY 2000 logic symbol† CLR CLK 1D 2D 3D 4D 5D 6D 7D 8D 1 R 11 C1 3 2 1D 4 5 7 6 8 9 13 12 14 15 17 16 18 19 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
PAGE 3
CD74FCT273 BiCMOS OCTAL D-TYPE FLIP-FLOP WITH RESET SCBS737A – JULY 2000 – REVISED JULY 2000 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† DC supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V DC input diode current, IIK (VI < –0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 4
CD74FCT273 BiCMOS OCTAL D-TYPE FLIP-FLOP WITH RESET SCBS737A – JULY 2000 – REVISED JULY 2000 timing requirements over recommended operating conditions (unless otherwise noted) (see Figure 1) MIN fclock Clock frequency tw Pulse duration tsu Setup time th Hold time CLR low 7 CLK high or low 7 Data before CLK↑ 3 CLR before CLK↑ 4 Data after CLK↑ 2 MAX UNIT 70 MHz ns ns ns switching characteristics over recommended operating conditions, CL = 50 pF (unless otherwise noted) (see Figure 1)
PAGE 5
CD74FCT273 BiCMOS OCTAL D-TYPE FLIP-FLOP WITH RESET SCBS737A – JULY 2000 – REVISED JULY 2000 PARAMETER MEASUREMENT INFORMATION 7V CL = 50 pF (see Note A) 500 Ω From Output Under Test Test Point From Output Under Test Open TEST GND CL = 50 pF (see Note A) 500 Ω S1 S1 Open 7V Open 7V tPLH/tPHL tPLZ/tPZL tPHZ/tPZH 500 Ω Open Drain LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 1.5 V 10% 90% 3V 1.
PAGE 6
PACKAGE OPTION ADDENDUM www.ti.
PAGE 7
PACKAGE OPTION ADDENDUM www.ti.com 23-Apr-2013 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.