Datasheet

7
NOTE:
14. For AC Series only: When V
CC
= 1.5V, R
L
= 1kΩ.
FIGURE 2. THREE-STATE PROPAGATION DELAY TIMES AND TEST CIRCUIT
FIGURE 3. PROPAGATION DELAY TIMES
DUT WITH
THREE-
STATE
OTHER
INPUTS
TIED HIGH
OR LOW
OUTPUT
DISABLE
GND (t
PHZ
, t
PZH
)
OPEN (t
PHL
, t
PLH
)
OUTPUT
R
L
C
L
50pF
2 V
CC
(t
PLZ
, t
PZL
)
(OPEN DRAIN)
500Ω
R
L
500Ω
OUT
INPUT LEVEL
90%
V
S
10%
GND
t
r
= 3ns
t
PZL
0.2 V
CC
V
OL
(≠ V
CC
)
0.8 V
CC
OUTPUTS
ENABLED
OUTPUTS
DISABLED
V
S
V
S
OUTPUTS
ENABLED
t
PLZ
t
PHZ
t
PZH
OUTPUTS
DISABLED
t
f
= 3ns
OUTPUT:
LOW TO OFF
TO LOW
OUTPUT:
HIGH TO OFF
TO HIGH
(NOTE 14)
t
r
= 3ns
INPUT
LEVEL
An
GND
Bn
t
PLH
t
f
= 3ns
90%
V
S
10%
V
S
t
PHL
DUT
OUTPUT
R
L
(NOTE)
OUTPUT
LOAD
500Ω
C
L
50pF
NOTE: For AC Series Only: When V
CC
= 1.5V, R
L
= 1kΩ.
FIGURE 4. PROPAGATION DELAY TIMES
AC ACT
Input Level V
CC
3V
Input Switching Voltage, V
S
0.5 V
CC
1.5V
Output Switching Voltage, V
S
0.5 V
CC
0.5 V
CC
CD54/74AC245, CD54/74ACT245