Datasheet

CD54ACT08, CD74ACT08
QUADRUPLE 2-INPUT POSITIVE-AND GATES
SCHS312B – JANUARY 2001 – REVISED JUNE 2002
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
t
h
t
su
10%10%
90% 90%
3 V
3 V
0 V
0 V
t
r
t
f
Reference
Input
Data
Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50% V
CC
50%
10%10%
90% 90%
3 V
V
OH
V
OL
0 V
t
r
t
f
Input
In-Phase
Output
t
PLH
t
PHL
50% V
CC
50%
10% 10%
90%90%
V
OH
V
OL
t
r
t
f
t
PHL
t
PLH
Out-of-Phase
Output
NOTES: A. C
L
includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z
O
= 50 Ω, t
r
= 3 ns, t
f
= 3 ns.
Phase relationships between waveforms are arbitrary.
D. For clock inputs, f
max
is measured with the input duty cycle at 50%.
E. The outputs are measured one at a time with one input transition per measurement.
F. t
PLH
and t
PHL
are the same as t
pd
.
G. t
PZL
and t
PZH
are the same as t
en
.
H. t
PLZ
and t
PHZ
are the same as t
dis
.
From Output
Under Test
C
L
= 50 pF
(see Note A)
LOAD CIRCUIT
S1
2 × V
CC
R1 = 500 Ω Open
GND
0 V
t
w
VOLTAGE WAVEFORMS
PULSE DURATION
Input
3 V
t
PLH
/t
PHL
t
PLZ
/t
PZL
t
PHZ
/t
PZH
Open
2 × V
CC
GND
TEST S1
Output
Control
Output
Waveform 1
S1 at 2 × V
CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
V
OL
V
OH
t
PZL
t
PZH
t
PLZ
t
PHZ
≈V
CC
0 V
20% V
CC
20% V
CC
80% V
CC
≈0 V
VOLTAGE WAVEFORMS
OUTPUT ENABLE AND DISABLE TIMES
80% V
CC
3 V
R2 = 500 Ω
VOLTAGE WAVEFORMS
RECOVERY TIME
3 V
0 V
CLR
Input
CLK
3 V
t
rec
0 V
1.5 V
1.5 V
1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V
1.5 V
1.5 V 1.5 V
Figure 1. Load Circuit and Voltage Waveforms