Datasheet

6
Propagation Delay,
MR to Qn
t
PLH
, t
PHL
1.5 - - 154 - - 169 ns
3.3 4.9 - 17.2 4.7 - 18.9 ns
5 3.5 - 12.3 3.4 - 13.5 ns
Input Capacitance C
I
- - -10- -10pF
Power Dissipation Capacitance C
PD
(Note 11)
- - 45 - - 45 - pF
ACT TYPES
Propagation Delay,
CP to Qn
t
PLH
, t
PHL
5
(Note 10)
3.5 - 12.3 3.4 - 13.5 ns
Propagation Delay,
MR to Qn
t
PLH
, t
PHL
5 3.5 - 12.3 3.4 - 13.5 ns
Input Capacitance C
I
- - -10- -10pF
Power Dissipation Capacitance C
PD
(Note 11)
- - 45 - - 45 - pF
NOTES:
8. Limits tested 100%.
9. 3.3V Min is at 3.6V, Max is at 3V.
10. 5V Min is at 5.5V, Max is at 4.5V.
11. C
PD
is used to determine the dynamic power consumption per flip-flop.
AC: P
D
= C
PD
V
CC
2
f
i
= ∑ (C
L
V
CC
2
f
o
)
ACT: P
D
=C
PD
V
CC
2
f
i
+ ∑ (C
L
V
CC
2
f
o
)+V
CC
∆I
CC
where f
i
= input frequency, f
o
= output frequency, C
L
= output load capacitance,
V
CC
= supply voltage.
FIGURE 1. PROPAGATION DELAY TIMES AND CLOCK
PULSE WIDTH
FIGURE 2. PREREQUISITE AND PROPAGATION DELAY
TIMES FOR MASTER RESET
Switching Specifications Input t
r
, t
f
= 3ns, C
L
= 50pF (Worst Case) (Continued)
PARAMETER SYMBOL V
CC
(V)
-40
o
C TO 85
o
C -55
o
C TO 125
o
C
UNITSMIN TYP MAX MIN TYP MAX
90%
t
f
t
r
V
S
V
S
V
S
V
S
V
S
t
PLH
t
PHL
t
W
10%
10%
CP
INPUT
LEVEL
Q
MR
CP
INPUT
LEVEL
V
S
Q
V
S
t
REM
V
S
V
S
t
PLH
t
W
GND
INPUT
(
Q)
CD54AC273, CD74AC273, CD54ACT273, CD74ACT273