Datasheet

6
FIGURE 1. THREE-STATE PROPAGATION DELAY WAVEFORMS AND TEST CIRCUIT
FIGURE 2. PROPAGATION DELAY TIMES
DUT
WITH
THREE-
STATE
OUTPUT
INPUT LEVEL
90%
V
S
10%
GND
t
f
= 3ns
t
PZL
t
PZH
t
PLZ
t
PHZ
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUT: LOW
TO OFF TO LOW
OUTPUT: HIGH
TO OFF TO HIGH
OTHER
INPUTS
(TIED HIGH
OR LOW)
OUTPUT
DISABLE
C
L
50pF
500Ω
†
R
L
500Ω†
R
L
OUT
V
S
0.2V
CC
V
OL
(≠ GND)
V
OH
(≠ V
CC
)
0.8 V
CC
V
S
GND (t
PHZ,
t
PZH
)
OUTPUTS
ENABLED
OPEN (t
PHL,
t
PLH
)
2 V
CC
(t
PLZ,
t
PZL
)
(OPEN DRAIN)
t
r
= 3ns
OUTPUT
DISABLE
†FOR AC SERIES ONLY: WHEN V
CC
= 1.5V, R
L
= 1kΩ
t
r
= 3ns t
f
= 3ns
I OR S
INPUT
OUTPUT Y
t
PLH
t
PHL
90%
V
S
10%
V
S
LEVEL
DUT
OUTPUT
R
L
(NOTE)
OUTPUT
LOAD
500Ω
C
L
50pF
NOTE: For AC Series Only: When V
CC
= 1.5V, R
L
= 1kΩ.
FIGURE 3. PROPAGATION DELAY TIMES
AC ACT
Input Level V
CC
3V
Input Switching Voltage, V
S
0.5 V
CC
1.5V
Output Switching Voltage, V
S
0.5 V
CC
0.5 V
CC
CD74AC253, CD54/74ACT253