Datasheet

CD54AC161, CD74AC161
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS239C – SEPTEMBER 1998 – REVISED MARCH 2003
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol, each D/T flip-flop
M1LD (Load)
Q (Output)
G2TE (Toggle Enable)
CK (Clock)
G4
3D
4R
1, 2T/1C3
D
(Inverted Data)
R
(Inverted Reset)
logic diagram, each D/T flip-flop (positive logic)
TG
TG
TG
TG
TG
TG
CK
LD
TE
LD
†
LD
†
D
R
CK
†
CK
†
CK
†
CK
†
Q
†
The origins of LD and CK are shown in the logic diagram of the overall device.