Datasheet

MOTOROLA CMOS LOGIC DATA
373
MC14512B
Figure 3. 3–State AC Test Circuit and Waveform
Test S1 S2 S3 S4
t
PHZ
Open Closed Closed Open
t
PLZ
Closed Open Open Closed
t
PZL
Closed Open Open Closed
t
PZH
Open Closed Closed Open
Switch Positions for 3–State Test
Z
DISABLE
INHIBIT
A
B
C
X0
X1
X2
X3
X4
X5
X6
X7
V
SS
PULSE
GENERATOR
V
DD
V
DD
C
L
1 k
S1
S2
V
SS
V
DD
S3
S4
V
SS
V
DD
V
OH
V
OL
20 ns
90%
50%
10%
t
PLZ
t
PZL
20 ns
DISABLE
INPUT
OUTPUT
OUTPUT
V
SS
V
OH
V
OL
10%
90%
90%
10%
t
PHZ
t
PZH
≈ 2.5 V @ V
DD
= 5 V,
10 V, AND 15 V
≈ 2 V @ V
DD
= 5 V
≈ 6 V @ V
DD
= 10 V
≈ 10 V @ V
DD
= 15 V
LOGIC DIAGRAM
13
12
11
1
2
3
4
5
6
7
9
X7
X6
X5
X4
X3
X2
X1
X0
B
C
A
15
10
14
DISABLE
INHIBIT
V
DD
Z
V
SS
1
1
IN
OUT
IN
2
OUT
2
TRANSMISSION
GATE
SELECTED
DEVICE
MC14512B
MC14512B
MC14512B
I
OD
I
TL
I
TL
I
L
LOAD
DATA
BUS
3–STATE MODE OF OPERATION
Output terminals of several MC14512B 8–Bit Data Selec-
tors can be connected to a single date bus as shown. One
MC14512B is selected by the 3–state control, and the re-
maining devices are disabled into a high–impedance “off”
state. The number of 8–bit data selectors, N, that may be
connected to a bus line is determined from the output drive
current, I
OD
, 3–state or disable output leakage current, I
TL
,
and the load current, I
L
, required to drive the bus line (includ-
ing fanout to other device inputs), and can be calculated by:
I
TL
N = + 1
I
OD
– I
L
N must be calculated for both high and low logic state of the
bus line.