CD4071BC,CD4071BM,CD4081BC,CD4081BM CD4071BM CD4071BC Quad 2-Input OR Buffered B Series Gate CD4081BM CD4081BC Quad 2-Input AND Buffered B Series Gate Literature Number: SNOS368A
CD4071BM/CD4071BC Quad 2-Input OR Buffered B Series Gate CD4081BM/CD4081BC Quad 2-Input AND Buffered B Series Gate General Description Features These quad gates are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. They have equal source and sink current capabilities and conform to standard B series output drive. The devices also have buffered outputs which improve transfer characteristics by providing very high gain.
Absolute Maximum Ratings (Notes 1 & 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Lead Temperature (TL) (Soldering, 10 seconds) Voltage at Any Pin b 0.5V to VDD a 0.5V Operating Conditions 700 mW 500 mW Operating Range (VDD) Operating Temperature Range (TA) CD4071BM, CD4081BM CD4071BC, CD4081BC Power Dissipation (PD) Dual-In-Line Small Outline VDD Range Storage Temperature (TS) b 0.
DC Electrical Characteristics CD4071BC/CD4081BC (Note 2) Parameter b 40§ C Conditions Min IDD Quiescent Device Current VDD e 5V VDD e 10V VDD e 15V VOL Low Level Output Voltage VDD e 5V VDD e 10V VDD e 15V High Level Output Voltage VDD e 5V VDD e 10V VDD e 15V VIL Low Level Input Voltage VDD e 5V, VO e 0.5V VDD e 10V, VO e 1.0V VDD e 15V, VO e 1.5V VIH High Level Input Voltage VDD e 5V, VO e 4.5V VDD e 10V, VO e 9.0V VDD e 15V, VO e 13.5V 3.5 7.0 11.
AC Electrical Characteristics* CD4081BC/CD4081BM TA e 25§ C, Input tr; tf e 20 ns, CL e 50 pF, RL e 200 kX, Typical temperature coefficient is 0.
Typical Performance Characteristics (Continued) TL/F/5977–13 FIGURE 7 TL/F/5977 – 15 TL/F/5977 – 14 FIGURE 9 TL/F/5977 – 17 bs ol TL/F/5977–16 et e FIGURE 8 O FIGURE 10 FIGURE 11 TL/F/5977 – 18 FIGURE 12 TL/F/5977 – 19 TL/F/5977 – 20 FIGURE 13 FIGURE 14 5
Schematic Diagrams CD4071B (/4 of device shown JeAaB Logical ‘‘1’’ e High Logical ‘‘0’’ e Low *All inputs protected by standard CMOS protection circuit. e TL/F/5977 – 2 et TL/F/5977–1 CD4081B (/4 of device shown bs ol JeA#B Logical ‘‘1’’ e High Logical ‘‘0’’ e Low *All inputs protected by standard CMOS protection circuit.
et e Physical Dimensions inches (millimeters) O bs ol Ceramic Dual-In-Line Package (J) Order Number CD4071BMJ, CD4071BCJ CD4081BMJ or CD4081BCJ NS Package Number J14A 7
e et Molded Dual-In-Line Package (N) Order Number CD4071BMN, CD4071BCN CD4081BMN or CD4081BCN NS Package Number N14A bs ol CD4071BM/CD4071BC Quad 2-Input OR Buffered B Series Gate CD4081BM/CD4081BC Quad 2-Input AND Buffered B Series Gate Physical Dimensions inches (millimeters) (Continued) LIFE SUPPORT POLICY O NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPOR
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