Datasheet

3
FIGURE 1. SCHEMATIC DIAGRAM FOR CD4070B
(1 OF 4 IDENTICAL GATES)
CD4070B TRUTH TABLE (1 OF 4 GATES)
ABJ
000
101
011
110
NOTE:
1 = High Level
0 = Low Level
J = A ⊕ B
V
DD
V
SS
V
SS
V
DD
V
DD
V
SS
V
SS
V
DD
p
n
p
n
p
n
p
p
n
p
n
J
3(4,10,11
)
B †
2(5,9,12)
A †
1(6,8,13)
† INPUTS PROTECTED
BY CMOS PROTECTION
NETWORK
FIGURE 2. SCHEMATIC DIAGRAM FOR CD4077B
(1 OF 4 IDENTICAL GATES)
CD4077B TRUTH TABLE (1 OF 4 GATES)
ABJ
001
100
010
111
NOTE:
1 = High Level
0 = Low Level
J = A ⊕ B
V
DD
V
SS
V
SS
V
DD
V
DD
V
SS
V
SS
V
DD
p
n
p
n
p
n
p
n
p
n
J
3(4,10,11
)
B †
2(5,9,12)
A †
1(6,8,13)
† INPUTS PROTECTED
BY CMOS PROTECTION
NETWORK
n
CD4070B, CD4077B