Datasheet

MOTOROLA CMOS LOGIC DATA
15
MC14001B
TYPICAL B–SERIES GATE CHARACTERISTICS (cont’d)
VOLTAGE TRANSFER CHARACTERISTICS
Figure 8. V
DD
= 5.0 Vdc Figure 9. V
DD
= 10 Vdc
1.0
3.0
5.0
4.0
2.0
0
1.0 3.0 5.04.02.00
0
0
V
in
, INPUT VOLTAGE (Vdc)
SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND
SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND
2.0
6.0
10
8.0
4.0
2.0 6.0 108.04.0
V
in
, INPUT VOLTAGE (Vdc)
V ,
out
OUTPUT VOLTAGE (Vdc)
V ,
out
OUTPUT VOLTAGE (Vdc)
Figure 10. V
DD
= 15 Vdc
0
0
SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND
2.0
6.0
10
8.0
4.0
2.0 6.0 108.04.0
V
in
, INPUT VOLTAGE (Vdc)
12
14
16
V ,
out
OUTPUT VOLTAGE (Vdc)
DC NOISE MARGIN
The DC noise margin is defined as the input voltage range
from an ideal “1” or “0” input level which does not produce
output state change(s). The typical and guaranteed limit val-
ues of the input values V
IL
and V
IH
for the output(s) to be at a
fixed voltage V
O
are given in the Electrical Characteristics
table. V
IL
and V
IH
are presented graphically in Figure 11.
Guaranteed minimum noise margins for both the “1” and
“0” levels =
1.0 V with a 5.0 V supply
2.0 V with a 10.0 V supply
2.5 V with a 15.0 V supply
Figure 11. DC Noise Immunity
V
out
V
O
V
O
V
IL
0
V
IH
V
in
V
DD
V
DD
V
out
V
O
V
O
V
IL
0
V
IH
V
in
V
DD
V
DD
(a) Inverting Function (b) Non–Inverting Function
V
SS
= 0 VOLTS DC