Datasheet

MOTOROLA CMOS LOGIC DATA
1
MC14069UB
The MC14069UB hex inverter is constructed with MOS P–channel and
N–channel enhancement mode devices in a single monolithic structure.
These inverters find primary use where low power dissipation and/or high
noise immunity is desired. Each of the six inverters is a single stage to
minimize propagation delays.
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky TTL Load Over the Rated Temperature Range
• Triple Diode Protection on All Inputs (see Page 5–2)
• Pin–for–Pin Replacement for CD4069UB
• Meets JEDEC UB Specifications
MAXIMUM RATINGS* (Voltages Referenced to V
SS
)
Symbol Parameter Value Unit
V
DD
DC Supply Voltage – 0.5 to + 18.0 V
V
in
, V
out
Input or Output Voltage (DC or Transient) – 0.5 to V
DD
+ 0.5 V
I
in
, I
out
Input or Output Current (DC or Transient),
per Pin
± 10 mA
P
D
Power Dissipation, per Package† 500 mW
T
stg
Storage Temperature – 65 to + 150
C
T
L
Lead Temperature (8–Second Soldering) 260
C
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C
CIRCUIT SCHEMATIC
(1/6 OF CIRCUIT SHOWN)
LOGIC DIAGRAM
13
11
9
5
3
1
12
10
8
6
4
2
V
DD
= PIN 14
V
SS
= PIN 7
V
DD
V
SS
OUTPUTINPUT*
* Double diode protection on all
inputs not shown.
Figure 1. Switching Time Test Circuit and Waveforms
PULSE
GENERATOR
V
DD
V
SS
7
INPUT
OUTPUT
C
L
14
20 ns 20 ns
V
DD
V
SS
V
OH
V
OL
t
THL
t
TLH
OUTPUT
INPUT
t
PHL
t
PLH
90%
50%
10%
90%
50%
10%
SEMICONDUCTOR TECHNICAL DATA
 Motorola, Inc. 1995
REV 3
1/94
L SUFFIX
CERAMIC
CASE 632
ORDERING INFORMATION
MC14XXXUBCP Plastic
MC14XXXUBCL Ceramic
MC14XXXUBD SOIC
T
A
= – 55° to 125°C for all packages.
P SUFFIX
PLASTIC
CASE 646
D SUFFIX
SOIC
CASE 751A
PIN ASSIGNMENT
11
12
13
14
8
9
105
4
3
2
1
7
6
OUT 5
IN 5
OUT 6
IN 6
V
DD
OUT 4
IN 4
OUT 2
IN 2
OUT 1
IN 1
V
SS
OUT 3
IN 3