Datasheet


   
SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Inputs
V
SS
Measure inputs sequentially to both V
DD
and V
SS
. Connect all unused inputs to either V
DD
or V
SS
. Measure control inputs only.
I
V
SS
V
DD
92CS-27555
Figure 16. Input Leakage-Current Test Circuit
V
DD
Channel 1
Channel 2
Channel 3
Channel 4
Channel 1
Channel 2
Channel 3
Channel 4
1/4 CD4066B
CD4066B
CD4066B
CD4018B
CD4018B
1/4 CD4066B
CD4001B
LPF
LPF
LPF
LPF
1
10237912
54
14
15
13
1
2
3
5
2
4
1
2
5
6
8
9
12
13
3
4
10
1
8
4
11
11
12
6
513
9
10
2
3
10 2 3 7 9 12
14
15
1
54
7
9
6
10
13 12 9 8 6 5 2 1
11
10 4
3
12 6 5 11
11 12
5
8
4
3
11
4
1
2
3
9
10
P
E
J
1
J
2
J
3
J
4
J
5
Q
2
Q
1
1/3 CD4049B
CD4001B
Signal
Inputs
Clock
Reset
Package Count
2 - CD4001B
1 - CD4049B
3 - CD4066B
2 - CD4018B
1/3 CD4049B
1/6 CD4049B
10 k
Signal
Outputs
P
E
J
1
J
2
J
3
J
4
J
5
Q
2
Q
1
External
Reset
Clock
Chan 1 Chan 2 Chan 3 Chan 4
V
DD
30% (V
DD
− V
SS
)
Clock
Maximum
Allowable
Signal Level
V
SS
92CM-30928
Ω
10 kΩ
10 kΩ
10 kΩ
10 kΩ
Figure 17. Four-Channel PAM Multiplex System Diagram