Datasheet

CD4051B-Q1, CD4052B-Q1, CD4053B-Q1
CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS
WITH LOGIC−LEVEL CONVERSION
SCHS354A − AUGUST 2004 − REVISED JANUARY 2008
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
MIN MAX UNIT
V
Supply voltage
5
20
V
V
DD
Supply voltage 5 20 V
T
A
Operating free-air temperature
−40
125 °C
electrical characteristics, V
SUPPLY
= ±5 V, A
V
= 1 V, R
L
= 100 Ω, unless otherwise noted
(see Note 2)
PARAMETER
TEST CONDITIONS
V
DD
LIMITS AT INDICATED
TEMPERATURES
UNIT
PARAMETER TEST CONDITIONS
V
DD
(V)
40°C
125°C
25°C
UNIT
(V)
−40°C
125°C
MIN TYP MAX
5 5 150 0.04 5
I
Quiescent device
10 10 300 0.04 10
A
I
DD
Quiescent
device
current
15 20 600 0.04 20
µA
20 100 3000 0.08 100
Signal Input (V
is
) and Output (V
os
)
Dit
V 0V V 0V
5 850 1300 470 1050
r
on
Drain-to-source
ON
-
state resistance
V
EE
= 0 V, V
SS
= 0 V,
V
IS
=0toV
DD
10 330 550 180 400
Ω
r
on
ON
-s
t
a
t
e res
i
s
t
ance
V
IS
= 0 to
V
DD
15 210 320 125 240
Ω
ON
-
state resistance
5 15
∆r
on
ON
-
state
resistance
difference between
V
EE
= 0 V, V
SS
= 0 V
10 10
Ω
∆r
on
difference
between
any two switches
V
EE
0
V,
V
SS
0
V
15 5
Ω
Input/output leakage
current (switch off)
Any channel OFF (MAX) or all channels
OFF (COM OUT/IN) (Max),
V
EE
= 0 V, V
SS
= 0 V, See Note 3
18 ±0.1 ±1 ±10
−5
±0.1 µA
C
is
Input capacitance V
EE
= −5 V, V
SS
= −5 V 5 5 pF
CD4051 30
C
os
Output capacitance V
EE
= −5 V, V
SS
= −5 V
CD4052
5
18
pF
C
os
Output
capacitance
V
EE
5
V,
V
SS
5
V
CD4053
5
9
pF
C
ios
Feedthrough
capacitance
V
EE
= −5 V, V
SS
= −5 V 5 0.2 pF
Propagation delay
V V R 200 kΩ
5 30 60
t
p
d
Propagation
delay
(signal input to
V
IS(p-p)
= V
DD
, R
L
= 200 kΩ,
C
L
=50pF t
r
t
f
=20ns
10 15 30
ns
t
pd
(signal
input
to
output)
C
L
=
50
p
F
,
t
r
,
t
f
=
20
ns
15 10 20
ns
NOTES: 2. Peak-to-peak voltage symmetrical about
V
DD
− V
EE
2
3. Determined by minimum feasible leakage measurement for automatic testing